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r8c/56e group, r8c/56f group, r8c/56g gr oup, r8c/56h group renesas mcu datasheet r01ds0042ej0200 rev.2.00 page 1 of 84 sep 05, 2012 1. overview 1.1 features the r8c/56e group, r8c/56f group, r8c/56g group, r8 c/56h group of single-chip microcontrollers (mcus) incorporate the r8c cpu core, which provides sophisticated instructions for a high level of efficiency. with 1 mbyte of address space, the cpu core is capable of execut ing instructions at high speed. in addition, it features a multiplier for high-speed arithmetic processing. power consumption is low, and additional power control is possible by selecting the operating mode. the r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group are also designed to ma ximize emi/ems performance. integration of many peripheral functions, including multif unction timer and serial interface on the same chip, reduces the number of system components. the r8c/56e group and r8c/56f group incorporate one channel of can module, id eal for the lan systems of automotive and factory automation applications. the r8c/56g group and r8c/56h group do not incorporate the can module. the r8c/56e group and r8c/56g group also have on-chip data flash (1 kb 4 blocks) with background operation (bgo) function. 1.1.1 applications automotive, etc. r01ds0042ej0200 rev.2.00 sep 05, 2012
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 2 of 84 sep 05, 2012 1.1.2 specifications tables 1.1 to 1.3 outline the r8c/56e group specifica tions. tables 1.4 to 1.6 outline the r8c/56f group specifications. tables 1.7 to 1.9 outline the r8c/56g group specifications. tables 1.10 to 1.12 outline the r8c/56h group specifications. table 1.1 r8c/56e group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.13 r8c/56e group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 59, selectable pull-up resistor ? peripheral mapping controller (pmc) allows either timer function priority or communication function priori ty pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator, pll operating), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (30 sources 10 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 (with prescaler) ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 42 ? transfer modes: 2 (normal mode, repeat mode)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 3 of 84 sep 05, 2012 table 1.2 r8c/56e group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb2_0 16 bits 1: 1 circuit integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 and rc_1 16 bits (with 4 capture/compare register s) 1: 2 circuits integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) (2 channels can be used only when 64 pins and timer function priority pin assignment are selected (only 1 channel for others)) timer rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode timer rf 16 bits 1 input capture function mo de (input capture function ), output compare mode (output compare function) timer rg 16 bits 1 timer mode (input capture functi on, output comp are function), pwm mode (output: 1 pin), phase counti ng mode (the counts of the 2-phase encoder can be automatically counted.) serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timer rj_0, rj_1, uart0_0, or uart0_1 used) can module can_0 1 channel: 16 mailboxes (iso11898-1 standard compliant) a/d converter resolution: 10 bits 16 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 2.7 v to 5.5 v ? program/erase endurance:10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function ? bgo (background operation) function (data flash)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 4 of 84 sep 05, 2012 note: 1. specify the k version if it is to be used. table 1.3 r8c/56e group specifications (3) item function description debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) current consumption typ. 14 ma (v cc = 5.0 v, f(cpu) = 32 mhz) operating ambient temperature -40 ? c to 85 ? c (j version) -40 ? c to 125 ? c (k version) (1) package 64-pin lqfp package code: plqp0064kb-a (previous code: 64p6q-a)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 5 of 84 sep 05, 2012 table 1.4 r8c/56f group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram refer to table 1.14 r8c/56f group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 59, selectable pull-up resistor ? peripheral mapping controller (pmc) allows either timer function priority or communication function priori ty pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator, pll operating), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (30 sources 10 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 (with prescaler) ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 42 ? transfer modes: 2 (normal mode, repeat mode)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 6 of 84 sep 05, 2012 table 1.5 r8c/56f group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb2_0 16 bits 1: 1 circuit integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 and rc_1 16 bits (with 4 capture/compare register s) 1: 2 circuits integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) (2 channels can be used only when 64 pins and timer function priority pin assignment are selected (only 1 channel for others)) timer rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode timer rf 16 bits 1 input capture function mo de (input capture function ), output compare mode (output compare function) timer rg 16 bits 1 timer mode (input capture functi on, output comp are function), pwm mode (output: 1 pin), phase counti ng mode (the counts of the 2-phase encoder can be automatically counted.) serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timer rj_0, rj_1, uart0_0, or uart0_1 used) can module can_0 1 channel: 16 mailboxes (iso11898-1 standard compliant) a/d converter resolution: 10 bits 16 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 2.7 v to 5.5 v ? program/erase endurance: 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 7 of 84 sep 05, 2012 note: 1. specify the k version if it is to be used. table 1.6 r8c/56f group specifications (3) item function description debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) current consumption typ. 14 ma (v cc = 5.0 v, f(cpu) = 32 mhz) operating ambient temperature -40 ? c to 85 ? c (j version) -40 ? c to 125 ? c (k version) (1) package 64-pin lqfp package code: plqp0064kb-a (previous code: 64p6q-a)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 8 of 84 sep 05, 2012 table 1.7 r8c/56g group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.15 r8c/56g group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 59, selectable pull-up resistor ? peripheral mapping controller (pmc) allows either timer function priority or communication function priori ty pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator, pll operating), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (30 sources 10 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 (with prescaler) ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 42 ? transfer modes: 2 (normal mode, repeat mode)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 9 of 84 sep 05, 2012 table 1.8 r8c/56g group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb2_0 16 bits 1: 1 circuit integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 and rc_1 16 bits (with 4 capture/compare register s) 1: 2 circuits integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) (2 channels can be used only when 64 pins and timer function priority pin assignment are selected (only 1 channel for others)) timer rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode timer rf 16 bits 1 input capture function mo de (input capture function ), output compare mode (output compare function) timer rg 16 bits 1 timer mode (input capture functi on, output comp are function), pwm mode (output: 1 pin), phase counti ng mode (the counts of the 2-phase encoder can be automatically counted.) serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timer rj_0, rj_1, uart0_0, or uart0_1 used) a/d converter resolution: 10 bits 16 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 2.7 v to 5.5 v ? program/erase endurance:10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function ? bgo (background operation) function (data flash)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 10 of 84 sep 05, 2012 note: 1. specify the k version if it is to be used. table 1.9 r8c/56g group specifications (3) item function description debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) current consumption typ. 14 ma (v cc = 5.0 v, f(cpu) = 32 mhz) operating ambient temperature -40 ? c to 85 ? c (j version) -40 ? c to 125 ? c (k version) (1) package 64-pin lqfp package code: plqp0064kb-a (previous code: 64p6q-a)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 11 of 84 sep 05, 2012 table 1.10 r8c/56h group specifications (1) item function description cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 31.25 ns (cpu clock = 32 mhz, vcc = 2.7 v to 5.5 v) ? multiplier: 16 bits 16 bits ? 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits ? 32 bits ? operating mode: single-chip mode (address space: 1 mbyte) memory rom, ram refer to table 1.16 r8c/56h group product list . voltage detection voltage detection circuit ? power-on reset ? voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) i/o ports programmable i/o ports ? input only: 1 ? cmos i/o: 59, selectable pull-up resistor ? peripheral mapping controller (pmc) allows either timer function priority or communication function priori ty pin assignment selection. clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, high-speed on-chip oscillator (wit h frequency adjustment function), low-speed on-chip oscillator, pll frequency synthesizer (up to 32 mhz), multiplied by 2, 4, 6, or 8 ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: divided by 1, 2, 4, 8, or 16 can be selected ? low-power mode: standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator, pll operating), wait mode, stop mode interrupts ? number of interrupt vectors: 69 ? external interrupt inputs: 9 (int 5, key input 4) ? priority levels: 7 event link controller (elc) ? events output from periph eral functions can be linked to events input to different peripheral functions. (30 sources 10 types of event link operations) ? events can be handled independently from interrupt requests. watchdog timer ? 14 bits 1 (with prescaler) ? selectable reset start function ? selectable low-speed on-chip oscillator for the watchdog timer dtc (data transfer controller) ? 1 channel ? activation sources: 42 ? transfer modes: 2 (normal mode, repeat mode)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 12 of 84 sep 05, 2012 table 1.11 r8c/56h group specifications (2) item function description timer timers rj_0 and rj_1 16 bits 1: 2 circuits integrated on-chip timer mode (periodic timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb2_0 16 bits 1: 1 circuit integrated on-chip timer mode (periodic timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one-shot generation mode timers rc_0 and rc_1 16 bits (with 4 capture/compare register s) 1: 2 circuits integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 3 pins), pwm2 mode (pwm output: 1 pin) (2 channels can be used only when 64 pins and timer function priority pin assignment are selected (only 1 channel for others)) timer rd_0 16 bits (with 4 capture/compare re gisters) 2: 1 circuit integrated on-chip timer mode (input capture function, output compare function), pwm mode (output: 6 pins), reset synchronous pwm mode (three-phase waveform output (6 pins), sawtooth wave modulation ), complementary pwm mode (three- phase waveform output (6 pins), triangular wave modulation), pwm3 mode (pwm output with fixe d period: 2 pins) timer re2 8 bits 1 compare match timer mode timer rf 16 bits 1 input capture function mo de (input capture function ), output compare mode (output compare function) timer rg 16 bits 1 timer mode (input capture functi on, output comp are function), pwm mode (output: 1 pin), phase counti ng mode (the counts of the 2-phase encoder can be automatically counted.) serial interface uart0_0 and uart0_1 2 channels clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode uart2 1 channel clock synchronous serial i/o mode, cl ock asynchronous serial i/o mode, special mode 3 (ie mode), multiprocessor communication mode clock synchronous serial interface (ssu) ssu_0 and ssu_1 2 channels (also used for the i 2 c bus) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) (i 2 c bus) i 2 c_0 and i 2 c_1 2 channels (also used for the ssu) (2 channels can be used only for communic ation function priority pin assignment (only 1 channel for others)) lin module hw-lin_0 and hw-lin_1 hardware lin 2 channels (timer rj_0, rj_1, uart0_0, or uart0_1 used) a/d converter resolution: 10 bits 16 channels, sample and hold function, sweep mode comparator b 2 circuits crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1), crc-16 (x 16 + x 15 + x 2 + 1) compliant flash memory ? program/erase voltage: vcc = 2.7 v to 5.5 v ? read voltage: vcc = 2.7 v to 5.5 v ? program/erase endurance: 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 13 of 84 sep 05, 2012 note: 1. specify the k version if it is to be used. table 1.12 r8c/56h group specifications (3) item function description debug functions ? 1-wire debug interface provided (dedicated hardware provided) ? hot plug connection is supported, allowing the debugger interface to be connected during user mode operation. operating frequency/ power supply voltage cpu clock = 32 mhz (vcc = 2.7 v to 5.5 v) current consumption typ. 14 ma (v cc = 5.0 v, f(cpu) = 32 mhz) operating ambient temperature -40 ? c to 85 ? c (j version) -40 ? c to 125 ? c (k version) (1) package 64-pin lqfp package code: plqp0064kb-a (previous code: 64p6q-a)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 14 of 84 sep 05, 2012 1.2 product list table 1.13 shows the r8c/56e group product list. figure 1.1 shows the r8c/56e group product part number structure. table 1.14 shows the r8c/56f group product list. figure 1.2 shows the r8c/56f group product part number structure. table 1.15 shows the r8c/56g gr oup product list. figure 1.3 shows the r8c/56g group product part number structure. table 1.16 shows the r8c/56h group product list. figure 1.4 shows the r8c/56h group product part number structure. figure 1.1 r8c/56e group product part number structure table 1.13 r8c/56e group product list part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f21566ejfp 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064kb-a j version r5f21567ejfp 48 kbytes 4 kbytes r5f21568ejfp 64 kbytes 6 kbytes r5f2156aejfp 96 kbytes 8 kbytes r5f2156cejfp 128 kbytes 10 kbytes r5f21566ekfp 32 kbytes 2.5 kbytes k version r5f21567ekfp 48 kbytes 4 kbytes r5f21568ekfp 64 kbytes 6 kbytes r5f2156aekfp 96 kbytes 8 kbytes r5f2156cekfp 128 kbytes 10 kbytes current of sep 2012 part no. r 5 f 21 56 c e j fp package type: fp: plqp0064kb-a (0.5 mm pin pitch, 10 ? 10 mm square body) classification j: operating ambient temperature -40c to 85c k: operating ambient temperature -40c to 125c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/56e group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 15 of 84 sep 05, 2012 figure 1.2 r8c/56f group product part number structure table 1.14 r8c/56f group product list part no. internal rom capacity internal ram capacity package type remarks program rom r5f21566fjfp 32 kbytes 2.5 kbytes plqp0064kb-a j version r5f21567fjfp 48 kbytes 4 kbytes r5f21568fjfp 64 kbytes 6 kbytes r5f2156afjfp 96 kbytes 8 kbytes r5f2156cfjfp 128 kbytes 10 kbytes r5f21566fkfp 32 kbytes 2.5 kbytes k version r5f21567fkfp 48 kbytes 4 kbytes r5f21568fkfp 64 kbytes 6 kbytes R5F2156AFKFP 96 kbytes 8 kbytes r5f2156cfkfp 128 kbytes 10 kbytes current of sep 2012 part no. r 5 f 21 56 c f j fp package type: fp: plqp0064kb-a (0.5 mm pin pitch, 10 ? 10 mm square body) classification j: operating ambient temperature -40c to 85c k: operating ambient temperature -40c to 125c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/56f group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 16 of 84 sep 05, 2012 figure 1.3 r8c/56g group product part number structure table 1.15 r8c/56g group product list part no. internal rom capacity internal ram capacity package type remarks program rom data flash r5f21566gjfp 32 kbytes 1 kbyte 4 2.5 kbytes plqp0064kb-a j version r5f21567gjfp 48 kbytes 4 kbytes r5f21568gjfp 64 kbytes 6 kbytes r5f2156agjfp 96 kbytes 8 kbytes r5f2156cgjfp 128 kbytes 10 kbytes r5f21566gkfp 32 kbytes 2.5 kbytes k version r5f21567gkfp 48 kbytes 4 kbytes r5f21568gkfp 64 kbytes 6 kbytes r5f2156agkfp 96 kbytes 8 kbytes r5f2156cgkfp 128 kbytes 10 kbytes current of sep 2012 part no. r 5 f 21 56 c g j fp package type: fp: plqp0064kb-a (0.5 mm pin pitch, 10 ? 10 mm square body) classification j: operating ambient temperature -40c to 85c k: operating ambient temperature -40c to 125c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/56g group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 17 of 84 sep 05, 2012 figure 1.4 r8c/56h group product part number structure table 1.16 r8c/56h group product list part no. internal rom capacity internal ram capacity package type remarks program rom r5f21566hjfp 32 kbytes 2.5 kbytes plqp0064kb-a j version r5f21567hjfp 48 kbytes 4 kbytes r5f21568hjfp 64 kbytes 6 kbytes r5f2156ahjfp 96 kbytes 8 kbytes r5f2156chjfp 128 kbytes 10 kbytes r5f21566hkfp 32 kbytes 2.5 kbytes k version r5f21567hkfp 48 kbytes 4 kbytes r5f21568hkfp 64 kbytes 6 kbytes r5f2156ahkfp 96 kbytes 8 kbytes r5f2156chkfp 128 kbytes 10 kbytes current of sep 2012 part no. r 5 f 21 56 c h j fp package type: fp: plqp0064kb-a (0.5 mm pin pitch, 10 ? 10 mm square body) classification j: operating ambient temperature -40c to 85c k: operating ambient temperature -40c to 125c availability of can, data flash e: can module: yes; data flash: yes f: can module: yes; data flash: no g: can module: no; data flash: yes h: can module: no; data flash: no rom capacity 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/56h group r8c/5x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 18 of 84 sep 05, 2012 1.3 block diagram figure 1.5 shows the block diagram. figure 1.5 block diagram dtc system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator low-speed on-chip oscillator (for watchdog timer) pll frequency synthesizer ram (3) multiplier timers timer rj (16 bits ? 2) timer rb2 (16 bits ? 1) timer rc (16 bits ? 2) timer rd (16 bits ? 2) timer re2 (8 bits ? 1) timer rf (16 bits ? 1) timer rg (16 bits ? 1) r8c cpu core memory r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. available in the r8c/56e group and the r8c/56f group only. 2. rom size varies with the product. 3. ram size varies with the product. a/d converter (10 bits ? 16 channels) uart2 (8 bits ? 1 channel) rom (2) peripheral functions watchdog timer (14 bits) lin module (2 channels) can module (1) (1 channel) synchronous serial communication unit (ssu/i 2 c) (8 bits ? 2 channels) event link controller crc calculator comparator b voltage detection circuit 5 port pc 4 port p9 7 port p8 8 port p0 8 port p1 8 port p3 5 1 port p4 7 port p5 8 port p6 port p2 8 pmc (peripheral mapping controller) pmc (peripheral mapping controller) uart0 (8 bits ? 2 channels)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 19 of 84 sep 05, 2012 1.4 pin assignment figure 1.6 shows pin assignment (top view). tables 1.17 to 1.22 list the pin name information by pin number. figure 1.6 pin assignment (top view) 1 3 4 5 6 7 8 9 10 11 12 2 13 14 15 16 r8c/56e group r8c/56f group r8c/56g group r8c/56h group plqp0064kb-a (64p6q-a) (top view) p0_7/an0/trcioc_0 p0_6/an1/trciod_0 p0_5/an2/clk2/trciob_0 p0_4/an3/tmre2o/trciob_0 p0_3/an4/clk_1/trciob_0 p0_2/an5/rxd_1/trcioa_0/trctrg_0/trjio_1/int2 p0_1/an6/txd_1/trcioa_0/trctrg_0/trjo_1 p0_0/an7/txd2/trcioa_0/trctrg_0 p6_4/rxd_1/int2 /trjio_1 p6_3/txd_1/trjo_1 p6_2/crx_0 (1) /clk_1 p6_1/ctx_0 (1) p6_0/tmre2o p5_7/trbo_0/trgiob p5_6/trjo_0/trgioa p3_2/int2 /trjio_0/int1 /trgclkb p8_4/trfo11 p8_5/trfo12 p8_6/clk2 p3_1/trbo_0/cts2 /rts2 p3_6/int1 /txd2/rxd2 p2_0/trdioa0_0/trdclk_0/int1 /txd2/rxd2/trciob_0 p2_1/trdiob0_0/trdioc0_0/trcioc_0 p2_2/trdioc0_0/trdiob0_0/trciod_0 p2_3/trdiod0_0 p2_4/trdioa1_0 (2) p2_5/trdiob1_0 (2) p2_6/trdioc1_0 (2) p2_7/trdiod1_0 (2) p3_3/ssi_0/int3 /trcclk_0/scs_0 /cts2 /rts2 /ivcmp3/trdiod0_0 p3_4/sda_0/scs_0 /trcioc_0/ssi_0/rxd2/txd2/ivref3/trdioc1_0/trdiob0_0 p3_5/scl_0/ssck_0/trciod_0/clk2/trdiod1_0/trdioa0_0/trdclk_0 p3_0/trjo_0/trgclka p4_2/vref mode p4_3 p4_4 reset p4_7/xout vss/avss p4_6/xin vcc/avcc p5_4/trciod_0 p5_3/trcioc_0 p5_2/trciob_0 p5_1/trcioa_0/trctrg_0 p5_0/trcclk_0 p3_7/sso_0/txd2/rxd2/trjo_0/sda_0/int3 /trcclk_0/trdioc0_0 p1_0/ki0 /an8/trciod_0/trdioa1_0 p1_1/ki1 /an9/trcioa_0/trctrg_0/trdiob1_0 p1_2/ki2 /an10/trciob_0/trdioc1_0 p1_3/ki3 /an11/trbo_0/trcioc_0/trdiod1_0 p1_4/txd_0/trcclk_0/anex0 p1_5/rxd_0/trjio_0/int1 /anex1 p1_6/clk_0/ssi_0/ivref1/anex2 p1_7/int1 /trjio_0/ivcmp1/anex3 (3) p4_5/int0 /rxd2 (3) p6_5/int4 /clk2/clk_1/trciob_0 (3) p6_6/int2 /txd2/trcioc_0 (3) p6_7/int3 /rxd2/trciod_0 (3) p8_0/trfo00 p8_1/trfo01 p8_2/trfo02 p8_3/trfo10/trfi 60 59 58 57 56 55 54 53 52 51 50 49 61 62 63 64 24 17 18 19 20 21 22 23 25 26 27 28 29 30 31 32 43 42 41 40 39 38 37 36 35 34 33 44 45 46 47 48 notes: 1. available in the r8c/56e group and the r8c/56f group only. 2. the pin functions are changed as follows by setting the pin assignment to communication function priority using the pmcsel re gister: p2_4/trdioa1_0 ? p9_4/ssi_1 p2_5/trdiob1_0 ? p9_5/sda_1/scs_1 p2_6/trdioc1_0 ? p9_6/scl_1/ssck_1/trbo_1 p2_7/trdiod1_0 ? p9_7/sso_1 3. the pin functions are changed as follows by setting the pin assi gnment to timer function priority using the pmcsel register: p1_7/int1 /trjio_0/ivcmp1/anex3 ? pc_0/trcclk_1 p4_5/int0 /rxd2 ? pc_1/trcioa_1/trctrg_1 p6_5/int4 /clk2/clk_1/trciob_0 ? pc_2/trciob_1 p6_6/int2 /txd2/trcioc_0 ? pc_3/trcioc_1 p6_7/int3 /rxd2/trciod_0 ? pc_4/trciod_1
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 20 of 84 sep 05, 2012 note: 1. pin assignments change depending on the pmc function. table 1.17 pin name information by pin number (int, urat0, and uart2) port pin no. int uart0 uart2 int0 int1 int2 int3 int4 txd_0 txd_1 rxd_0 rxd_1 clk_0 clk_1 txd2 rxd2 cts2 rts2 clk2 p0_0 56 txd2 p0_1 55 txd_1 p0_2 54 int2 rxd_1 p0_3 53 clk_1 p0_4 52 p0_5 51 clk2 p0_6 50 p0_7 49 p1_0 48 p1_1 47 p1_2 46 p1_3 45 p1_4 44 txd_0 p1_5 43 int1 rxd_0 p1_6 42 clk_0 p1_7 41 (1) int1 p2_0 27 int1 txd2 rxd2 p2_1 26 p2_2 25 p2_3 24 p2_4 23 (1) p2_5 22 (1) p2_6 21 (1) p2_7 20 (1) p3_0 1 p3_1 29 cts2 rts2 p3_2 64 int1 int2 p3_3 19 int3 cts2 rts2 p3_4 18 txd2 rxd2 p3_5 17 clk2 p3_6 28 int1 txd2 rxd2 p3_7 16 int3 txd2 rxd2 p4_2 2 p4_3 4 p4_4 5 p4_5 40 (1) int0 rxd2 p4_6 9 p4_7 7 p5_0 15 p5_1 14 p5_2 13 p5_3 12 p5_4 11 p5_6 63 p5_7 62 p6_0 61 p6_1 60 p6_2 59 clk_1 p6_3 58 txd_1 p6_4 57 int2 rxd_1 p6_5 39 (1) int4 clk_1 clk2 p6_6 38 (1) int2 txd2 p6_7 37 (1) int3 rxd2 p8_0 36 p8_1 35 p8_2 34 p8_3 33 p8_4 32 p8_5 31 p8_6 30 clk2 p9_4 23 (1) p9_5 22 (1) p9_6 21 (1) p9_7 20 (1) pc_0 41 (1) pc_1 40 (1) pc_2 39 (1) pc_3 38 (1) pc_4 37 (1)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 21 of 84 sep 05, 2012 notes: 1. available in the r8c/56e group and the r8c/56f group only. 2. pin assignments change depending on the pmc function. table 1.18 pin name information by pin number (can and ssu/i 2 c) port pin no. can (1) ssu/i 2 c ctx_0 crx_0 scl_0 scl_1 sda_0 sda_1 ssi_0 ssi_1 scs_0 scs_1 ssck_0 ssck_1 sso_0 sso_1 p0_0 56 p0_1 55 p0_2 54 p0_3 53 p0_4 52 p0_5 51 p0_6 50 p0_7 49 p1_0 48 p1_1 47 p1_2 46 p1_3 45 p1_4 44 p1_5 43 p1_6 42 ssi_0 p1_7 41 (2) p2_0 27 p2_1 26 p2_2 25 p2_3 24 p2_4 23 (2) p2_5 22 (2) p2_6 21 (2) p2_7 20 (2) p3_0 1 p3_1 29 p3_2 64 p3_3 19 ssi_0 scs_0 p3_4 18 sda_0 ssi_0 scs_0 p3_5 17 scl_0 ssck_0 p3_6 28 p3_7 16 sda_0 sso_0 p4_2 2 p4_3 4 p4_4 5 p4_5 40 (2) p4_6 9 p4_7 7 p5_0 15 p5_1 14 p5_2 13 p5_3 12 p5_4 11 p5_6 63 p5_7 62 p6_0 61 p6_1 60 ctx_0 p6_2 59 crx_0 p6_3 58 p6_4 57 p6_5 39 (2) p6_6 38 (2) p6_7 37 (2) p8_0 36 p8_1 35 p8_2 34 p8_3 33 p8_4 32 p8_5 31 p8_6 30 p9_4 23 (2) ssi_1 p9_5 22 (2) sda_1 scs_1 p9_6 21 (2) scl_1 ssck_1 p9_7 20 (2) sso_1 pc_0 41 (2) pc_1 40 (2) pc_2 39 (2) pc_3 38 (2) pc_4 37 (2)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 22 of 84 sep 05, 2012 note: 1. pin assignments change depending on the pmc function. table 1.19 pin name information by pin number (timer rc) port pin no. timer rc trcclk_0 trcclk_1 trcioa_0 trciob_0 trcioc_0 trciod_0 trctrg _0 trcclk_1 trcioa_1 trciob_1 trcioc_1 trciod_1 trctrg_1 p0_0 56 trcioa_0 trctrg_0 p0_1 55 trcioa_0 trctrg_0 p0_2 54 trcioa_0 trctrg_0 p0_3 53 trciob_0 p0_4 52 trciob_0 p0_5 51 trciob_0 p0_6 50 trciod_0 p0_7 49 trcioc_0 p1_0 48 trciod_0 p1_1 47 trcioa_0 trctrg_0 p1_2 46 trciob_0 p1_3 45 trcioc_0 p1_4 44 trcclk_0 p1_5 43 p1_6 42 p1_7 41 (1) p2_0 27 trciob_0 p2_1 26 trcioc_0 p2_2 25 trciod_0 p2_3 24 p2_4 23 (1) p2_5 22 (1) p2_6 21 (1) p2_7 20 (1) p3_0 1 p3_1 29 p3_2 64 p3_3 19 trcclk_0 p3_4 18 trcioc_0 p3_5 17 trciod_0 p3_6 28 p3_7 16 trcclk_0 p4_2 2 p4_3 4 p4_4 5 p4_5 40 (1) p4_6 9 p4_7 7 p5_0 15 trcclk_0 p5_1 14 trcioa_0 trctrg_0 p5_2 13 trciob_0 p5_3 12 trcioc_0 p5_4 11 trciod_0 p5_6 63 p5_7 62 p6_0 61 p6_1 60 p6_2 59 p6_3 58 p6_4 57 p6_5 39 (1) trciob_0 p6_6 38 (1) trcioc_0 p6_7 37 (1) trciod_0 p8_0 36 p8_1 35 p8_2 34 p8_3 33 p8_4 32 p8_5 31 p8_6 30 p9_4 23 (1) p9_5 22 (1) p9_6 21 (1) p9_7 20 (1) pc_0 41 (1) trcclk_1 pc_1 40 (1) trcioa_1 trctrg_1 pc_2 39 (1) trciob_1 pc_3 38 (1) trcioc_1 pc_4 37 (1) trciod_1
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 23 of 84 sep 05, 2012 note: 1. pin assignments change depending on the pmc function. table 1.20 pin name information by pin number (timer rd) port pin no. timer rd trdclk_0 trdioa0_0 trdiob0_0 trdioc0_0 trdiod0_0 trdioa1_0 trdiob1_0 trdioc1_0 trdiod1_0 p0_0 56 p0_1 55 p0_2 54 p0_3 53 p0_4 52 p0_5 51 p0_6 50 p0_7 49 p1_0 48 trdioa1_0 p1_1 47 trdiob1_0 p1_2 46 trdioc1_0 p1_3 45 trdiod1_0 p1_4 44 p1_5 43 p1_6 42 p1_7 41 (1) p2_0 27 trdclk_0 trdioa0_0 p2_1 26 trdiob0_0 trdioc0_0 p2_2 25 trdiob0_0 trdioc0_0 p2_3 24 trdiod0_0 p2_4 23 (1) trdioa1_0 p2_5 22 (1) trdiob1_0 p2_6 21 (1) trdioc1_0 p2_7 20 (1) trdiod1_0 p3_0 1 p3_1 29 p3_2 64 p3_3 19 trdiod0_0 p3_4 18 trdiob0_0 trdioc1_0 p3_5 17 trdclk_0 trdioa0_0 trdiod1_0 p3_6 28 p3_7 16 trdioc0_0 p4_2 2 p4_3 4 p4_4 5 p4_5 40 (1) p4_6 9 p4_7 7 p5_0 15 p5_1 14 p5_2 13 p5_3 12 p5_4 11 p5_6 63 p5_7 62 p6_0 61 p6_1 60 p6_2 59 p6_3 58 p6_4 57 p6_5 39 (1) p6_6 38 (1) p6_7 37 (1) p8_0 36 p8_1 35 p8_2 34 p8_3 33 p8_4 32 p8_5 31 p8_6 30 p9_4 23 (1) p9_5 22 (1) p9_6 21 (1) p9_7 20 (1) pc_0 41 (1) pc_1 40 (1) pc_2 39 (1) pc_3 38 (1) pc_4 37 (1)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 24 of 84 sep 05, 2012 note: 1. pin assignments change depending on the pmc function. table 1.21 pin name information by pin number (timer rj, timer rb2, timer re2, and timer rf) port pin no. timer rj timer rb2 timer re2 timer rf trjo_0 trjo_1 trjio_0 trjio_1 trbo_0 tmre2o trfi trfo00 trfo01 trfo02 trfo10 trfo11 trfo12 p0_0 56 p0_1 55 trjo_1 p0_2 54 trjio_1 p0_3 53 p0_4 52 tmre2o p0_5 51 p0_6 50 p0_7 49 p1_0 48 p1_1 47 p1_2 46 p1_3 45 trbo_0 p1_4 44 p1_5 43 trjio_0 p1_6 42 p1_7 41 (1) trjio_0 p2_0 27 p2_1 26 p2_2 25 p2_3 24 p2_4 23 (1) p2_5 22 (1) p2_6 21 (1) p2_7 20 (1) p3_0 1 trjo_0 p3_1 29 trbo_0 p3_2 64 trjio_0 p3_3 19 p3_4 18 p3_5 17 p3_6 28 p3_7 16 trjo_0 p4_2 2 p4_3 4 p4_4 5 p4_5 40 (1) p4_6 9 p4_7 7 p5_0 15 p5_1 14 p5_2 13 p5_3 12 p5_4 11 p5_6 63 trjo_0 p5_7 62 trbo_0 p6_0 61 tmre2o p6_1 60 p6_2 59 p6_3 58 trjo_1 p6_4 57 trjio_1 p6_5 39 (1) p6_6 38 (1) p6_7 37 (1) p8_0 36 trfo00 p8_1 35 trfo01 p8_2 34 trfo02 p8_3 33 trfi trfo10 p8_4 32 trfo11 p8_5 31 trfo12 p8_6 30 p9_4 23 (1) p9_5 22 (1) p9_6 21 (1) p9_7 20 (1) pc_0 41 (1) pc_1 40 (1) pc_2 39 (1) pc_3 38 (1) pc_4 37 (1)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 25 of 84 sep 05, 2012 note: 1. pin assignments change depending on the pmc function. table 1.22 pin name information by pin number (timer rg and others) port pin no. timer rg others trgclka trgclkb trgioa trggiob p0_0 56 an7 p0_1 55 an6 p0_2 54 an5 p0_3 53 an4 p0_4 52 an3 p0_5 51 an2 p0_6 50 an1 p0_7 49 an0 p1_0 48 ki0 an8 p1_1 47 ki1 an9 p1_2 46 ki2 an10 p1_3 45 ki3 an11 p1_4 44 anex0 p1_5 43 anex1 p1_6 42 ivref1 anex2 p1_7 41 (1) ivcmp1 anex3 p2_0 27 p2_1 26 p2_2 25 p2_3 24 p2_4 23 (1) p2_5 22 (1) p2_6 21 (1) p2_7 20 (1) p3_0 1 trgclka p3_1 29 p3_2 64 trgclkb p3_3 19 ivcmp3 p3_4 18 ivref3 p3_5 17 p3_6 28 p3_7 16 p4_2 2 vref p4_3 4 p4_4 5 p4_5 40 (1) p4_6 9 xin p4_7 7 xout p5_0 15 p5_1 14 p5_2 13 p5_3 12 p5_4 11 p5_6 63 trgioa p5_7 62 trggiob p6_0 61 p6_1 60 p6_2 59 p6_3 58 p6_4 57 p6_5 39 (1) p6_6 38 (1) p6_7 37 (1) p8_0 36 p8_1 35 p8_2 34 p8_3 33 p8_4 32 p8_5 31 p8_6 30 p9_4 23 (1) p9_5 22 (1) p9_6 21 (1) p9_7 20 (1) pc_0 41 (1) pc_1 40 (1) pc_2 39 (1) pc_3 38 (1) pc_4 37 (1)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 26 of 84 sep 05, 2012 1.5 pin functions tables 1.23 and 1.24 list pin functions. note: 1. contact the oscillator manufacture r for oscillation characteristics. table 1.23 pin functions (1) item pin name i/o description power supply input vcc, vss ? apply 2.7 v through 5.5 v to the vcc pin when the cpu clock = 32 mhz. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply input for the a/d converter. connect a capacitor between pins avcc and avss. reset input reset i applying a low level to this pin resets the mcu. mode mode i connect this pin to the vcc pin via a resistor. xin clock input xin i i/o for th e xin clock generation circuit. connect a ceramic resonator or a crystal oscillator between pins xin and xout. (1) to use an external clock, input it to the xin pin and leave the xout pin open. xin clock output xout i/o int interrupt input int0 to int4 i int interrupt input. key input interrupt ki0 to ki3 i key input interrupt input. timers rj_0 and rj_1 trjio_0, trj io_1 i/o input/output for timer rj. trjo_0, trjo_1 o output for timer rj. timer rb2_0 trbo_0 o output for timer rb2. timers rc_0 and rc_1 trcclk_0, trcclk_1 i external clock input. trctrg_0, trctrg_1 i ext ernal trigger input. trcioa_0, trciob_0, trcioc_0, trciod_0, trcioa_1, trciob_1, trcioc_1, trciod_1 i/o input/output for timer rc. timer rd_0 trdioa0_0, trdioa1_0, trdiob0_0, trdiob1_0, trdioc0_0, trdioc1_0, trdiod0_0, trdiod1_0 i/o input/output for timer rd. trdclk_0 i external clock input. timer re2 tmre2o o divided clock output. timer rf trfo00, trfo10, trfo01, trfo11, trfo02, trfo12 o output for timer rf. trfi i input for timer rf. timer rg trgioa, trgiob i/o input/output for timer rg. trgclka, trgclkb i external clock input. serial interface (uart0) clk_0, clk_1 i/o transf er clock input/output. rxd_0, rxd_1 i serial data input. txd_0, txd_1 o serial data output.
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 1. overview r01ds0042ej0200 rev.2.00 page 27 of 84 sep 05, 2012 note: 1. available in the r8c/56e group and the r8c/56f group only. table 1.24 pin functions (2) item pin name i/o description serial interface (uart2) cts2 i input for transmission control. rts2 o output for reception control. rxd2 i serial data input. txd2 o serial data output. clk2 i/o transfer clock input/output. synchronous serial communication unit (ssu_0, ssu_1) ssi_0, ssi_1 i/o data input/output. scs_0 , scs_1 i/o chip-select input/output. ssck_0, ssck_1 i/o clock input/output. sso_0, sso_1 i/o data input/output. i 2 c bus (i 2 c_0 and i 2 c_1) scl_0, scl_1 i/o clock input/output. sda_0, sda_1 i/o data input/output. can module (can_0) (1) crx_0 i data input for can. ctx_0 o data output for can. reference voltage input vref i reference voltage input for the a/d converter. a/d converter an0 to an11, anex0 to anex3 i analog input for the a/d converter. comparator b ivcmp1, ivcmp3 i analo g voltage input for comparator b. ivref1, ivref3 i reference voltage input for comparator b. i/o ports p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_3 to p4_7, p5_0 to p5_4, p5_6, p5_7, p6_0 to p6_7, p8_0 to p8_6, p9_4 to p9_7, pc_0 to pc_4 i/o 8-bit cmos input/output ports. each port has an i/o select direction register, enabling switching input and output for each pin. for input ports, the presence or absence of a pull-up resistor can be selected by a program. all ports can be used as led drive (high drive) ports. input port p4_2 i input-only port.
r8c/56e group, r8c/56f group, r8 c/56g group, r8c/56h group 2. ce ntral processing unit (cpu) r01ds0042ej0200 rev.2.00 page 28 of 84 sep 05, 2012 2. central processi ng unit (cpu) figure 2.1 shows the 13 cpu registers. the registers r0, r1 , r2, r3, a0, a1, and fb form a single register bank. the cpu has two register banks. figure 2.1 cpu registers the higher 4 bits of intb are intbh and the lower 16 bits of intb are intbl. interrupt table register data registers (1) address registers (1) frame base register (1) user stack pointer interrupt stack pointer static base register program counter carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bits processor interrupt priority level reserved bit note: 1. these registers form a single register bank. the cpu has two register banks. flag register r3 r2 b31 b0 b15 fb r2 r3 a0 a1 r0h (r0 high-order byte) r1h (r1 high-order byte) r0l (r0 low-order byte) r1l (r1 low-order byte) intbh b19 b0 intbl b15 pc b19 b0 b15 b0 usp isp sb b15 b0 flg b15 b0 b8 b7 cdzsboiu ipl b8 b7
r8c/56e group, r8c/56f group, r8 c/56g group, r8c/56h group 2. ce ntral processing unit (cpu) r01ds0042ej0200 rev.2.00 page 29 of 84 sep 05, 2012 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, arithmetic, and logic operations. the same applies to r1 through r3. r0 can be split into high-order (r0h) and low-order (r0l) re gisters to be used separate ly as 8-bit data registers. the same applies to r1h and r1l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). similarly, r3 and r1 can be us ed as a 32-bit data register. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 f unctions in the same manner as a0. a1 can be combined with a0 and used as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register used for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the start address of a re locatable interrupt vector table. 2.5 program counter (pc) pc is a 20-bit register that indicates the address of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wi de. the u flag of the flg register is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register used for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register th at indicates the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated in th e arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. it must only be set to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0. otherwise it is set to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value. otherwise it is set to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation resu lts in an overflow. otherwise it is set to 0.
r8c/56e group, r8c/56f group, r8 c/56g group, r8c/56h group 2. ce ntral processing unit (cpu) r01ds0042ej0200 rev.2.00 page 30 of 84 sep 05, 2012 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i fl ag is 0, and are enabled when the i flag is 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is 0. usp is selected when the u flag is 1. the u flag is set to 0 when a hardware interrupt request is acknowledged or the int instruc tion for a software interrupt numbered from 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. if a requested interrupt has higher priority than ipl, the interrupt is enabled. 2.8.10 reserved bit the write value must be 0. the read value is undefined.
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 31 of 85 sep 05, 2012 3. address space 3.1 r8c/56e group memory map figure 3.1 shows the r8c/56e group memory map. the r8c/56e group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal rom (data flash) is allocated at addresses 07000h to 07fffh. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.1 r8c/56e group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr internal rom (data flash) (1) 002ffh 00400h 07000h 07fffh 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (2) notes: 1. data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. addresses 06800h to 06fffh are used for the can, dtc, and other sfr areas. 3. the blank areas are reserved. no access is allowed. part number capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r5f21566ejfp, r5f21566ekfp r5f21567ejfp, r5f21567ekfp r5f21568ejfp, r5f21568ekfp r5f2156aejfp, r5f2156aekfp r5f2156cejfp, r5f2156cekfp
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 32 of 85 sep 05, 2012 3.2 r8c/56f group memory map figure 3.2 shows the r8c/56f group memory map. the r8c/56f group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.2 r8c/56f group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr 002ffh 00400h 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (1) notes: 1. addresses 06800h to 06fffh are used for the can, dtc, and other sfr areas. 2. the blank areas are reserved. no access is allowed. part number capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r5f21566fjfp, r5f21566fkfp r5f21567fjfp, r5f21567fkfp r5f21568fjfp, r5f21568fkfp r5f2156afjfp, R5F2156AFKFP r5f2156cfjfp, r5f2156cfkfp
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 33 of 85 sep 05, 2012 3.3 r8c/56g group memory map figure 3.3 shows the r8c/56g group memory map. th e r8c/56g group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal rom (data flash) is allocated at addresses 07000h to 07fffh. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.3 r8c/56g group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr internal rom (data flash) (1) 002ffh 00400h 07000h 07fffh 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (2) notes: 1. data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. addresses 06800h to 06fffh are used for the dtc and other sfr areas. 3. the blank areas are reserved. no access is allowed. part number capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r5f21566gjfp, r5f21566gkfp r5f21567gjfp, r5f21567gkfp r5f21568gjfp, r5f21568gkfp r5f2156agjfp, r5f2156agkfp r5f2156cgjfp, r5f2156cgkfp
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 34 of 85 sep 05, 2012 3.4 r8c/56h group memory map figure 3.4 shows the r8c/56h group memory map. th e r8c/56h group has a 1-mbyte address space from addresses 00000h to fffffh. up to 32 kbytes of the in ternal rom (program rom) is allocated at lower addresses, beginning with a ddress 0ffffh. the area in excess of 32 kbytes is allocated at higher addresses, beginning with address 10000h. for example, a 64-kbyte inte rnal rom is allocated at addresses 08000h to 17fffh. the fixed interrupt vector ta ble is allocated at addresse s 0ffdch to 0ffffh. the start address of each interrupt routine is stored here. the internal ram is allocated at hi gher addresses, beginning with address 00400h. for example, a 6-kbyte internal ram is allocated at addresses 00400h to 01bffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is calle d or when an interrupt request is acknowledged. special function registers (sfrs) ar e allocated at addresses 00000h to 02fffh and addresses 06800h to 06fffh. peripheral function control registers are allocated here. a ll unallocated locations within the sfrs are reserved and cannot be accessed by users. figure 3.4 r8c/56h group memory map 0xxxxh 00000h internal rom (program rom) internal ram sfr 002ffh 00400h 0yyyyh 0ffffh fffffh watchdog timer, oscillation stop detection, voltage monitor undefined instruction overflow brk instruction address match single-step address break (reserved) reset 0ffffh 0ffdch internal rom (program rom) zzzzzh 06fffh 06800h sfr (1) notes: 1. addresses 06800h to 06fffh are used for the dtc and other sfr areas. 2. the blank areas are reserved. no access is allowed. part number capacity address 0yyyyh internal rom address 0xxxxh capacity internal ram address zzzzzh 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 08000h 08000h 08000h 08000h 08000h 0ffffh 13fffh 17fffh 1ffffh 27fffh 00dffh 013ffh 01bffh 023ffh 02bffh 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes r5f21566hjfp, r5f21566hkfp r5f21567hjfp, r5f21567hkfp r5f21568hjfp, r5f21568hkfp r5f2156ahjfp, r5f2156ahkfp r5f2156chjfp, r5f2156chkfp
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 35 of 85 sep 05, 2012 3.5 special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tabl es 3.1 to 3.23 list the sfr information. table 3.24 lists the id code area, option function select area. x: undefined notes: 1. the blank areas are reserved. no access is allowed. 2. depends on the csproini bit in the ofs register. 3. depends on the lvdasi bit in the ofs register. table 3.1 sfr information (1) (1) address symbol register name after reset remarks 00000h 00001h 00002h 00003h 00004h pm0 processor mode register 0 00h 00005h pm1 processor mode register 1 10000000b 00006h 00007h prcr protect register 00h 00008h cm0 system clock control register 0 00101000b 00009h cm1 system clock control register 1 00100000b 0000ah ocd oscillation stop detection register 00h 0000bh cm3 system clock control register 3 00h 0000ch cm4 system clock control register 4 00000001b 0000dh 0000eh 0000fh pclkr1 peripheral clock select register 1 00h 00010h 00011h 00012h fra0 high-speed on-chip oscillator control register 0 00h 00013h 00014h fra2 high-speed on-chip oscillator control register 2 00h 00015h 00016h 00017h 00018h 00019h 0001ah 0001bh 0001ch plc0 pll control register 0 00010010b 0001dh 0001eh 0001fh 00020h risr reset interrupt select register 10000000b or 00000000b (note 2) 00021h wdtr watchdog timer reset register ffh 00022h wdts watchdog timer start register ffh 00023h wdtc watchdog timer control register 011 11111b 00024h cspr count source protection mode register 10000000b or 00000000b (note 2) 00025h 00026h 00027h 00028h rstfr reset source determination register 00xxxxxxb 00029h 0002ah 0002bh 0002ch svdc stby vdc power control register 00h 0002dh 0002eh 0002fh 00030h cmpa voltage monitor circuit control register 00h 00031h vcac voltage monitor circuit edge select register 00h 00032h ocvrefcr on-chip reference voltage control register 00h 00033h 00034h vca2 voltage detection register 2 00000000b or 00100000b (note 3) 00035h 00036h vd1ls voltage detection 1 level select register 00000111b 00037h 00038h vw0c voltage monitor 0 circuit control register 1100xx10b or 1100xx11b (note 3) 00039h vw1c voltage monitor 1 circuit control register 10001010b
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 36 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.2 sfr information (2) (1) address symbol register name after reset remarks 0003ah vw2c voltage monitor 2 circuit control register 10001010b 0003bh 0003ch 0003dh 0003eh 0003fh 00040h 00041h fmrdyic interrupt control register 00h 00042h trjic_1 interrupt control register 00h 00043h 00044h 00045h 00046h int4ic interrupt control register 00h 00047h trcic_0 interrupt control register 00h 00048h trd0ic_0 interrupt control register 00h 00049h trd1ic_0 interrupt control register 00h 0004ah tre2ic interrupt control register 00h 0004bh u2tic interrupt control register 00h 0004ch u2ric interrupt control register 00h 0004dh kupic interrupt control register 00h 0004eh adic interrupt control register 00h 0004fh ssuic_0/iicic_0 interrupt control register 00h 00050h trfic interrupt control register 00h 00051h u0tic_0 interrupt control register 00h 00052h u0ric_0 interrupt control register 00h 00053h u0tic_1 interrupt control register 00h 00054h u0ric_1 interrupt control register 00h 00055h int2ic interrupt control register 00h 00056h trjic_0 interrupt control register 00h 00057h 00058h trb2ic_0 interrupt control register 00h 00059h int1ic interrupt control register 00h 0005ah int3ic interrupt control register 00h 0005bh 0005ch 0005dh int0ic interrupt control register 00h 0005eh u2bcnic interrupt control register 00h 0005fh 00060h 00061h 00062h 00063h 00064h 00065h 00066h 00067h 00068h 00069h 0006ah 0006bh trgic interrupt control register 00h 0006ch canrxic_0 interrupt control register 00h 0006dh cantxic_0 interrupt control register 00h 0006eh caneric_0 interrupt control register 00h 0006fh 00070h 00071h 00072h vcmp1ic interrupt control register 00h 00073h vcmp2ic interrupt control register 00h 00074h 00075h 00076h 00077h 00078h 00079h ssuic_1/iicic_1 interrupt control register 00h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 37 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.3 sfr information (3) (1) address symbol register name after reset remarks 0007ah 0007bh 0007ch 0007dh 0007eh 0007fh trcic_1 interrupt control register 00h 00080h u0mr_0 uart0_0 transmit/receive mode register 00h 00081h u0brg_0 uart0_0 bit rate register xxh 00082h u0tb_0 uart0_0 transmit buffer register xxh 00083h xxh 00084h u0c0_0 uart0_0 transmit/receive control register 0 00001000b 00085h u0c1_0 uart0_0 transmit/receive control register 1 00000010b 00086h u0rb_0 uart0_0 receive buffer register xxxxh 00087h 00088h u0ir_0 uart0_0 interrupt flag and enable register 00h 00089h 0008ah 0008bh 0008ch lincr2_0 lin_0 special function register 00h 0008dh 0008eh linct_0 lin_0 control register 00h 0008fh linst_0 lin_0 status register 00h 00090h u0mr_1 uart0_1 transmit/receive mode register 00h 00091h u0brg_1 uart0_1 bit rate register xxh 00092h u0tb_1 uart0_1 transmit buffer register xxh 00093h xxh 00094h u0c0_1 uart0_1 transmit/receive control register 0 00001000b 00095h u0c1_1 uart0_1 transmit/receive control register 1 00000010b 00096h u0rb_1 uart0_1 receive buffer register xxxxh 00097h 00098h u0ir_1 uart0_1 interrupt flag and enable register 00h 00099h 0009ah 0009bh 0009ch lincr2_1 lin_1 special function register 00h 0009dh 0009eh linct_1 lin_1 control register 00h 0009fh linst_1 lin_1 status register 00h 000a0h 000a1h 000a2h 000a3h 000a4h 000a5h 000a6h 000a7h 000a8h 000a9h 000aah 000abh 000ach 000adh 000aeh 000afh 000b0h 000b1h 000b2h 000b3h 000b4h 000b5h 000b6h 000b7h 000b8h 000b9h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 38 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.4 sfr information (4) (1) address symbol register name after reset remarks 000bah 000bbh 000bch 000bdh 000beh 000bfh 000c0h u2mr uart2 transmit/receive mode register 00h 000c1h u2brg uart2 bit rate register 00h 000c2h u2tb uart2 transmit buffer register 00h 000c3h 00h 000c4h u2c0 uart2 transmit/receive control register 0 00001000b 000c5h u2c1 uart2 transmit/receive control register 1 00000010b 000c6h u2rb uart2 receive buffer register 0000h 000c7h 000c8h u2rxdf uart2 digital filter function select register 00h 000c9h 000cah 000cbh 000cch 000cdh 000ceh 000cfh 000d0h u2smr5 uart2 special mode register 5 00h 000d1h 000d2h 000d3h 000d4h 000d5h u2smr3 uart2 special mode register 3 00h 000d6h 000d7h u2smr uart2 special mode register 00h 000d8h 000d9h 000dah 000dbh 000dch 000ddh 000deh 000dfh 000e0h iiccr_0 i 2 c_0 control register 00001110b 000e1h ssbr_0 ss_0 bit counter register 11111000b 000e2h sitdr_0 si_0 transmit data register ffh 000e3h ffh 000e4h sirdr_0 si_0 receive data register ffh 000e5h ffh 000e6h sicr1_0 si_0 control register 1 00h 000e7h sicr2_0 si_0 control register 2 01111101b 000e8h simr1_0 si_0 mode register 1 00010000b 000e9h sier_0 si_0 interrupt enable register 00h 000eah sisr_0 si_0 status register 00h 000ebh simr2_0 si_0 mode register 2 00h 000ech 000edh 000eeh 000efh 000f0h iiccr_1 i 2 c_1 control register 00001110b 000f1h ssbr_1 ss_1 bit counter register 1 1111000b 000f2h sitdr_1 si_1 transmit data register ffh 000f3h ffh 000f4h sirdr_1 si_1 receive data register ffh 000f5h ffh 000f6h sicr1_1 si_1 control register 1 00h 000f7h sicr2_1 si_1 control register 2 01111101b 000f8h simr1_1 si_1 mode register 1 00010000b 000f9h sier_1 si_1 interrupt enable register 00h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 39 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.5 sfr information (5) (1) address symbol register name after reset remarks 000fah sisr_1 si_1 status register 00h 000fbh simr2_1 si_1 mode register 2 00h 000fch 000fdh 000feh 000ffh 00100h 00101h 00102h 00103h 00104h 00105h 00106h 00107h 00108h 00109h 0010ah 0010bh 0010ch 0010dh 0010eh 0010fh 00110h trj_0 timer rj_0 counter register ffffh 00111h 00112h trjcr_0 timer rj_0 control register 00h 00113h trjioc_0 timer rj_0 i/o control register 00h 00114h trjmr_0 timer rj_0 mode register 00h 00115h trjisr_0 timer rj_0 event pin select register 00h 00116h 00117h 00118h trj_1 timer rj_1 counter register ffffh 00119h 0011ah trjcr_1 timer rj_1 control register 00h 0011bh trjioc_1 timer rj_1 i/o control register 00h 0011ch trjmr_1 timer rj_1 mode register 00h 0011dh trjisr_1 timer rj_1 event pin select register 00h 0011eh 0011fh 00120h 00121h 00122h 00123h 00124h 00125h 00126h 00127h 00128h 00129h 0012ah 0012bh 0012ch 0012dh 0012eh 0012fh 00130h trbcr_0 timer rb2_0 control register 00h 00131h trbocr_0 timer rb2_0 one-shot control register 00h 00132h trbioc_0 timer rb2_0 i/o control register 00h 00133h trbmr_0 timer rb2_0 mode register 00h 00134h trbpre_0 trbprsc_0 timer rb2_0 prescaler register timer rb2_0 primary/secondary register (lower 8 bits) ffh 00135h trbpr_0 timer rb2_0 primary register timer rb2_0 primary register (higher 8 bits) ffh 00136h trbsc_0 timer rb2_0 secondary register timer rb2_0 secondary register (higher 8 bits) ffh 00137h trbir_0 timer rb2_0 interrupt request register 00h 00138h trccnt_0 timer rc_0 counter 0000h 00139h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 40 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.6 sfr information (6) (1) address symbol register name after reset remarks 0013ah trcgra_0 timer rc_0 general register a ffffh 0013bh 0013ch trcgrb_0 timer rc_0 general register b ffffh 0013dh 0013eh trcgrc_0 timer rc_0 general register c ffffh 0013fh 00140h trcgrd_0 timer rc_0 general register d ffffh 00141h 00142h trcmr_0 timer rc_0 mode register 01001000b 00143h trccr1_0 timer rc_0 control register 1 00h 00144h trcier_0 timer rc_0 interrupt enable register 01110000b 00145h trcsr_0 timer rc_0 status register 01110000b 00146h trcior0_0 timer rc_0 i/o control register 0 10001000b 00147h trcior1_0 timer rc_0 i/o control register 1 10001000b 00148h trccr2_0 timer rc_0 control register 2 00011000b 00149h trcdf_0 timer rc_0 digital filter function select register 00h 0014ah trcoer_0 timer rc_0 output enable register 01111111b 0014bh trcadcr_0 timer rc_0 a/d conversion trigger control register 11110000b 0014ch trcopr_0 timer rc_0 output waveform manipulation register 00h 0014dh trcelccr_0 timer rc_0 elc cooperation control register 00h 0014eh 0014fh 00150h 00151h 00152h 00153h 00154h 00155h 00156h 00157h 00158h trccnt_1 timer rc_1 counter 0000h 00159h 0015ah trcgra_1 timer rc_1 general register a ffffh 0015bh 0015ch trcgrb_1 timer rc_1 general register b ffffh 0015dh 0015eh trcgrc_1 timer rc_1 general register c ffffh 0015fh 00160h trcgrd_1 timer rc_1 general register d ffffh 00161h 00162h trcmr_1 timer rc_1 mode register 01001000b 00163h trccr1_1 timer rc_1 control register 1 00h 00164h trcier_1 timer rc_1 interrupt enable register 01110000b 00165h trcsr_1 timer rc_1 status register 01110000b 00166h trcior0_1 timer rc_1 i/o control register 0 10001000b 00167h trcior1_1 timer rc_1 i/o control register 1 10001000b 00168h trccr2_1 timer rc_1 control register 2 00011000b 00169h trcdf_1 timer rc_1 digital filter function select register 00h 0016ah trcoer_1 timer rc_1 output enable register 01111111b 0016bh 0016ch trcopr_1 timer rc_1 output waveform manipulation register 00h 0016dh trcelccr_1 timer rc_1 elc cooperation control register 00h 0016eh 0016fh 00170h tresec timer re2 counter data register 00h 00171h tremin timer re2 compare data register 00h 00172h 00173h 00174h 00175h 00176h 00177h trecr timer re2 control register 00000100b 00178h trecsr timer re2 count source select register 00001000b 00179h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 41 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.7 sfr information (7) (1) address symbol register name after reset remarks 0017ah treifr timer re2 interrupt flag register 00h 0017bh treier timer re2 interrupt enable register 00h 0017ch 0017dh 0017eh 0017fh treprc timer re2 protect register 00h 00180h trdelccr_0 timer rd_0 elc cooperation control register 00h 00181h 00182h trdadcr_0 timer rd_0 trigger control register 00h 00183h trdstr_0 timer rd_0 start register 1 1111100b 00184h trdmr_0 timer rd_0 mode register 00001110b 00185h trdpmr_0 timer rd_0 pwm mode register 10001000b 00186h trdfcr_0 timer rd_0 function control register 10000000b 00187h trdoer1_0 timer rd_0 output master enable register 1 ffh 00188h trdoer2_0 timer rd_0 output master enable register 2 011 11111b 00189h trdocr_0 timer rd_0 output control register 00h 0018ah trddf0_0 timer rd_0 digital filter function select register 0 00h 0018bh trddf1_0 timer rd_0 digital filter function select register 1 00h 0018ch 0018dh 0018eh 0018fh 00190h trdcr0_0 timer rd_0 control register 0 00h 00191h trdiora0_0 timer rd_0 i/o control register a0 10001000b 00192h trdiorc0_0 timer rd_0 i/o control register c0 10001000b 00193h trdsr0_0 timer rd_0 status register 0 11100000b 00194h trdier0_0 timer rd_0 interrupt enable register 0 11100000b 00195h trdpocr0_0 timer rd_0 pwm mode output level control register 0 1 1111000b 00196h trd0_0 timer rd_0 counter 0 0000h 00197h 00198h trdgra0_0 timer rd_0 general register a0 ffffh 00199h 0019ah trdgrb0_0 timer rd_0 general register b0 ffffh 0019bh 0019ch trdgrc0_0 timer rd_0 general register c0 ffffh 0019dh 0019eh trdgrd0_0 timer rd_0 general register d0 ffffh 0019fh 001a0h trdcr1_0 timer rd_0 control register 1 00h 001a1h trdiora1_0 timer rd_0 i/o control register a1 10001000b 001a2h trdiorc1_0 timer rd_0 i/o control register c1 10001000b 001a3h trdsr1_0 timer rd_0 status register 1 11000000b 001a4h trdier1_0 timer rd_0 interrupt enable register 1 11100000b 001a5h trdpocr1_0 timer rd_0 pwm mode output level control register 1 11111000b 001a6h trd1_0 timer rd_0 counter 1 0000h 001a7h 001a8h trdgra1_0 timer rd_0 general register a1 ffffh 001a9h 001aah trdgrb1_0 timer rd_0 general register b1 ffffh 001abh 001ach trdgrc1_0 timer rd_0 general register c1 ffffh 001adh 001aeh trdgrd1_0 timer rd_0 general register d1 ffffh 001afh 001b0h trf timer rf register 0000h 001b1h 001b2h trfout timer rf output control register 00h 001b3h trfin timer rf input control register 00h 001b4h trfsr timer rf status register 00h 001b5h 001b6h trfier timer rf interrupt enable register 00h 001b7h 001b8h 001b9h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 42 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.8 sfr information (8) (1) address symbol register name after reset remarks 001bah trfcr0 timer rf control register 0 00h 001bbh trfcr1 timer rf control register 1 00h 001bch trfm0 timer rf capture compare 0 register 0000h 001bdh 001beh trfm1 timer rf compare 1 register ffffh 001bfh 001c0h 001c1h 001c2h 001c3h 001c4h 001c5h 001c6h 001c7h 001c8h 001c9h 001cah 001cbh 001cch 001cdh 001ceh 001cfh 001d0h 001d1h 001d2h 001d3h 001d4h 001d5h 001d6h 001d7h 001d8h 001d9h 001dah 001dbh 001dch 001ddh 001deh 001dfh 001e0h 001e1h 001e2h 001e3h 001e4h 001e5h 001e6h 001e7h 001e8h 001e9h 001eah 001ebh 001ech 001edh 001eeh 001efh 001f0h trgmr timer rg mode register 00h 001f1h trgcntc timer rg counter control register 00h 001f2h trgcr timer rg control register 10000000h 001f3h trgier timer rg interrupt enable register 11110000h 001f4h trgsr timer rg status register 11100000h 001f5h trgior timer rg i/o control register 00h 001f6h trg timer rg counter 0000h 001f7h 001f8h trggra timer rg general register a ffffh 001f9h 001fah trggrb timer rg general register b ffffh 001fbh 001fch trggrc timer rg general register c ffffh 001fdh 001feh trggrd timer rg general register d ffffh 001ffh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 43 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.9 sfr information (9) (1) address symbol register name after reset remarks 00200h ad0 a/d register 0 00h 00201h 00h 00202h ad1 a/d register 1 00h 00203h 00h 00204h ad2 a/d register 2 00h 00205h 00h 00206h ad3 a/d register 3 00h 00207h 00h 00208h ad4 a/d register 4 00h 00209h 00h 0020ah ad5 a/d register 5 00h 0020bh 00h 0020ch ad6 a/d register 6 00h 0020dh 00h 0020eh ad7 a/d register 7 00h 0020fh 00h 00210h 00211h 00212h 00213h 00214h admod a/d mode register 00h 00215h adinsel a/d input select register 11000000b 00216h adcon0 a/d control register 0 00h 00217h adcon1 a/d control register 1 00h 00218h 00219h 0021ah 0021bh 0021ch 0021dh 0021eh 0021fh 00220h 00221h 00222h 00223h 00224h 00225h 00226h 00227h 00228h intcmp comparator b control register 0 00h 00229h 0022ah 0022bh 0022ch 0022dh 0022eh 0022fh 00230h inten external input enable register 0 00h 00231h inten1 external input enable register 1 00h 00232h intf int input filter select register 0 00h 00233h intf1 int input filter select register 1 00h 00234h intpol int input polarity switch register 00h 00235h 00236h kien key input interrupt enable register 00h 00237h 00238h mstcr0 module standby control register 0 00h 00239h mstcr1 module standby control register 1 00h 0023ah mstcr2 module standby control register 2 00h 0023bh mstcr3 module standby control register 3 00h 0023ch 0023dh 0023eh 0023fh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 44 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.10 sfr information (10) (1) address symbol register name after reset remarks 00240h 00241h 00242h 00243h 00244h 00245h 00246h 00247h 00248h 00249h 0024ah 0024bh 0024ch 0024dh 0024eh 0024fh 00250h 00251h 00252h fst flash memory status register 10000x00b 00253h 00254h fmr0 flash memory control register 0 00h 00255h fmr1 flash memory control register 1 00h 00256h fmr2 flash memory control register 2 00h 00257h 00258h 00259h 0025ah 0025bh 0025ch 0025dh 0025eh 0025fh 00260h aiadr0l address match interrupt address 0l register xxxxh 00261h 00262h aiadr0h address match interrupt address 0h register 0000xxxxb 00263h aien0 address match interrupt enable 0 register 00h 00264h aiadr1l address match interrupt address 1l register xxxxh 00265h 00266h aiadr1h address match interrupt address 1h register 0000xxxxb 00267h aien1 address match interrupt enable 1 register 00h 00268h 00269h 0026ah 0026bh 0026ch 0026dh 0026eh 0026fh 00270h 00271h 00272h 00273h 00274h 00275h 00276h 00277h 00278h 00279h 0027ah 0027bh 0027ch 0027dh 0027eh 0027fh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 45 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.11 sfr information (11) (1) address symbol register name after reset remarks 00280h dtctl dtc activation control register 00h 00281h 00282h 00283h 00284h 00285h 00286h 00287h 00288h dtcen0 dtc activation enable register 0 00h 00289h dtcen1 dtc activation enable register 1 00h 0028ah dtcen2 dtc activation enable register 2 00h 0028bh dtcen3 dtc activation enable register 3 00h 0028ch dtcen4 dtc activation enable register 4 00h 0028dh dtcen5 dtc activation enable register 5 00h 0028eh dtcen6 dtc activation enable register 6 00h 0028fh 00290h crcsar sfr snoop address register 0000h 00291h 00292h crcmr crc control register 00h 00293h 00294h crcd crc data register 0000h 00295h 00296h crcin crc input register 00h 00297h 00298h 00299h 0029ah 0029bh 0029ch 0029dh 0029eh 0029fh 002a0h trj_0sr timer rj_0 pin select register 00h 002a1h trj_1sr timer rj_1 pin select register 00h 002a2h 002a3h 002a4h trbsr timer rb2 pin select register 00h 002a5h trcclksr timer rcclk pin select register 00h 002a6h trc_0sr0 timer rc_0 pin select register 0 00h 002a7h trc_0sr1 timer rc_0 pin select register 1 00h 002a8h trc_1sr timer rc_1 pin select register 00h 002a9h trd_0sr0 timer rd_0 pin select register 0 00h 002aah trd_0sr1 timer rd_0 pin select register 1 00h 002abh 002ach 002adh timsr timer pin select register 00h 002aeh u_0sr uart0_0 pin select register 00h 002afh u_1sr uart0_1 pin select register 00h 002b0h 002b1h 002b2h u2sr0 uart2 pin select register 0 00h 002b3h u2sr1 uart2 pin select register 1 00h 002b4h ssuiic_0sr ssu/iic_0 pin select register 00h 002b5h 002b6h intsr0 int interrupt input pin select register 0 00h 002b7h 002b8h 002b9h pinsr i/o function pin select register 00h 002bah 002bbh 002bch 002bdh 002beh pmcsel pin assignment select register 00h 002bfh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 46 of 85 sep 05, 2012 note: 1. the blank areas are reserved. no access is allowed. table 3.12 sfr information (12) (1) address symbol register name after reset remarks 002c0h pur0 pull-up control register 0 00h 002c1h pur1 pull-up control register 1 00h 002c2h pur2 pull-up control register 2 00h 002c3h pur3 pull-up control register 3 00h 002c4h 002c5h 002c6h 002c7h 002c8h p1drr port p1 drive capacity control register 00h 002c9h p2drr port p2 drive capacity control register 00h 002cah 002cbh pcdrr port pc drive c apacity contro l register 00h 002cch drr0 drive capacity control register 0 00h 002cdh drr1 drive capacity control register 1 00h 002ceh drr2 drive capacity control register 2 00h 002cfh 002d0h vlt0 input threshold control register 0 00h 002d1h vlt1 input threshold control register 1 00h 002d2h vlt2 input threshold control register 2 00h 002d3h vlt3 input threshold control register 3 00h 002d4h 002d5h 002d6h 002d7h 002d8h 002d9h 002dah 002dbh 002dch 002ddh 002deh 002dfh 002e0h port0 port p0 register xxh 002e1h port1 port p1 register xxh 002e2h pd0 port p0 direction register 00h 002e3h pd1 port p1 direction register 00h 002e4h port2 port p2 register xxh 002e5h port3 port p3 register xxh 002e6h pd2 port p2 direction register 00h 002e7h pd3 port p3 direction register 00h 002e8h port4 port p4 register xxh 002e9h port5 port p5 register xxh 002eah pd4 port p4 direction register 00h 002ebh pd5 port p5 direction register 00h 002ech port6 port p6 register xxh 002edh 002eeh pd6 port p6 direction register 00h 002efh 002f0h port8 port p8 register xxh 002f1h port9 port p9 register xxh 002f2h pd8 port p8 direction register 00h 002f3h pd9 port p9 direction register 00h 002f4h 002f5h 002f6h 002f7h 002f8h portc port pc register xxh 002f9h 002fah pdc port pc direction register 00h 002fbh 002fch 002fdh 002feh 002ffh 00300h to 003ffh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 47 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.13 sfr information (13) (1) address symbol register name after reset remarks 00400h to 02bffh on-chip ram on-chip ram 02c00h to 069ffh 06a00h elselr0 event output destination select register 0 00h 06a01h elselr1 event output destination select register 1 00h 06a02h elselr2 event output destination select register 2 00h 06a03h elselr3 event output destination select register 3 00h 06a04h elselr4 event output destination select register 4 00h 06a05h 06a06h 06a07h 06a08h elselr8 event output destination select register 8 00h 06a09h elselr9 event output destination select register 9 00h 06a0ah elselr10 event output destination select register 10 00h 06a0bh elselr11 event output destination select register 11 00h 06a0ch elselr12 event output destination select register 12 00h 06a0dh elselr13 event output destination select register 13 00h 06a0eh elselr14 event output destination select register 14 00h 06a0fh elselr15 event output destination select register 15 00h 06a10h elselr16 event output destination select register 16 00h 06a11h elselr17 event output destination select register 17 00h 06a12h elselr18 event output destination select register 18 00h 06a13h elselr19 event output destination select register 19 00h 06a14h elselr20 event output destination select register 20 00h 06a15h elselr21 event output destination select register 21 00h 06a16h elselr22 event output destination select register 22 00h 06a17h elselr23 event output destination select register 23 00h 06a18h elselr24 event output destination select register 24 00h 06a19h elselr25 event output destination select register 25 00h 06a1ah elselr26 event output destination select register 26 00h 06a1bh elselr27 event output destination select register 27 00h 06a1ch elselr28 event output destination select register 28 00h 06a1dh 06a1eh 06a1fh 06a20h 06a21h 06a22h 06a23h 06a24h 06a25h 06a26h 06a27h 06a28h 06a29h 06a2ah 06a2bh 06a2ch 06a2dh elselr45 event output destination select register 45 00h 06a2eh elselr46 event output destination select register 46 00h 06a2fh elselr47 event output destination select register 47 00h 06a30h elselr48 event output destination select register 48 00h 06a31h to 06bffh 06c00h area for storing dtc transfer vector 0 xxh 06c01h area for storing dtc transfer vector 1 xxh 06c02h area for storing dtc transfer vector 2 xxh 06c03h area for storing dtc transfer vector 3 xxh 06c04h area for storing dtc transfer vector 4 xxh 06c05h 06c06h 06c07h 06c08h area for storing dtc transfer vector 8 xxh 06c09h area for storing dtc transfer vector 9 xxh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 48 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.14 sfr information (14) (1) address symbol register name after reset remarks 06c0ah area for storing dtc transfer vector 10 xxh 06c0bh area for storing dtc transfer vector 11 xxh 06c0ch area for storing dtc transfer vector 12 xxh 06c0dh area for storing dtc transfer vector 13 xxh 06c0eh area for storing dtc transfer vector 14 xxh 06c0fh area for storing dtc transfer vector 15 xxh 06c10h area for storing dtc transfer vector 16 xxh 06c11h area for storing dtc transfer vector 17 xxh 06c12h area for storing dtc transfer vector 18 xxh 06c13h area for storing dtc transfer vector 19 xxh 06c14h 06c15h 06c16h area for storing dtc transfer vector 22 xxh 06c17h area for storing dtc transfer vector 23 xxh 06c18h area for storing dtc transfer vector 24 xxh 06c19h area for storing dtc transfer vector 25 xxh 06c1ah area for storing dtc transfer vector 26 xxh 06c1bh area for storing dtc transfer vector 27 xxh 06c1ch area for storing dtc transfer vector 28 xxh 06c1dh area for storing dtc transfer vector 29 xxh 06c1eh area for storing dtc transfer vector 30 xxh 06c1fh area for storing dtc transfer vector 31 xxh 06c20h area for storing dtc transfer vector 32 xxh 06c21h area for storing dtc transfer vector 33 xxh 06c22h 06c23h 06c24h 06c25h 06c26h area for storing dtc transfer vector 38 xxh 06c27h area for storing dtc transfer vector 39 xxh 06c28h 06c29h 06c2ah area for storing dtc transfer vector 42 xxh 06c2bh area for storing dtc transfer vector 43 xxh 06c2ch area for storing dtc transfer vector 44 xxh 06c2dh area for storing dtc transfer vector 45 xxh 06c2eh area for storing dtc transfer vector 46 xxh 06c2fh area for storing dtc transfer vector 47 xxh 06c30h area for storing dtc transfer vector 48 xxh 06c31h area for storing dtc transfer vector 49 xxh 06c32h area for storing dtc transfer vector 50 xxh 06c33h area for storing dtc transfer vector 51 xxh 06c34h area for storing dtc transfer vector 52 xxh 06c35h 06c36h 06c37h 06c38h 06c39h 06c3ah 06c3bh 06c3ch 06c3dh 06c3eh 06c3fh 06c40h dtccr0 dtc control register 0 xxh 06c41h dtbls0 dtc block size register 0 xxh 06c42h dtcct0 dtc transfer count register 0 xxh 06c43h dtrld0 dtc transfer count reload register 0 xxh 06c44h dtsar0 dtc source address register 0 xxxxh 06c45h 06c46h dtdar0 dtc destination address register 0 xxxxh 06c47h 06c48h dtccr1 dtc control register 1 xxh 06c49h dtbls1 dtc block size register 1 xxh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 49 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.15 sfr information (15) (1) address symbol register name after reset remarks 06c4ah dtcct1 dtc transfer count register 1 xxh 06c4bh dtrld1 dtc transfer count reload register 1 xxh 06c4ch dtsar1 dtc source address register 1 xxxxh 06c4dh 06c4eh dtdar1 dtc destination address register 1 xxxxh 06c4fh 06c50h dtccr2 dtc control register 2 xxh 06c51h dtbls2 dtc block size register 2 xxh 06c52h dtcct2 dtc transfer count register 2 xxh 06c53h dtrld2 dtc transfer count reload register 2 xxh 06c54h dtsar2 dtc source address register 2 xxxxh 06c55h 06c56h dtdar2 dtc destination address register 2 xxxxh 06c57h 06c58h dtccr3 dtc control register 3 xxh 06c59h dtbls3 dtc block size register 3 xxh 06c5ah dtcct3 dtc transfer count register 3 xxh 06c5bh dtrld3 dtc transfer count reload register 3 xxh 06c5ch dtsar3 dtc source address register 3 xxxxh 06c5dh 06c5eh dtdar3 dtc destination address register 3 xxxxh 06c5fh 06c60h dtccr4 dtc control register 4 xxh 06c61h dtbls4 dtc block size register 4 xxh 06c62h dtcct4 dtc transfer count register 4 xxh 06c63h dtrld4 dtc transfer count reload register 4 xxh 06c64h dtsar4 dtc source address register 4 xxxxh 06c65h 06c66h dtdar4 dtc destination address register 4 xxxxh 06c67h 06c68h dtccr5 dtc control register 5 xxh 06c69h dtbls5 dtc block size register 5 xxh 06c6ah dtcct5 dtc transfer count register 5 xxh 06c6bh dtrld5 dtc transfer count reload register 5 xxh 06c6ch dtsar5 dtc source address register 5 xxxxh 06c6dh 06c6eh dtdar5 dtc destination address register 5 xxxxh 06c6fh 06c70h dtccr6 dtc control register 6 xxh 06c71h dtbls6 dtc block size register 6 xxh 06c72h dtcct6 dtc transfer count register 6 xxh 06c73h dtrld6 dtc transfer count reload register 6 xxh 06c74h dtsar6 dtc source address register 6 xxxxh 06c75h 06c76h dtdar6 dtc destination address register 6 xxxxh 06c77h 06c78h dtccr7 dtc control register 7 xxh 06c79h dtbls7 dtc block size register 7 xxh 06c7ah dtcct7 dtc transfer count register 7 xxh 06c7bh dtrld7 dtc transfer count reload register 7 xxh 06c7ch dtsar7 dtc source address register 7 xxxxh 06c7dh 06c7eh dtdar7 dtc destination address register 7 xxxxh 06c7fh 06c80h dtccr8 dtc control register 8 xxh 06c81h dtbls8 dtc block size register 8 xxh 06c82h dtcct8 dtc transfer count register 8 xxh 06c83h dtrld8 dtc transfer count reload register 8 xxh 06c84h dtsar8 dtc source address register 8 xxxxh 06c85h 06c86h dtdar8 dtc destination address register 8 xxxxh 06c87h 06c88h dtccr9 dtc control register 9 xxh 06c89h dtbls9 dtc block size register 9 xxh 06c8ah dtcct9 dtc transfer count register 9 xxh 06c8bh dtrld9 dtc transfer count reload register 9 xxh 06c8ch dtsar9 dtc source address register 9 xxxxh 06c8dh 06c8eh dtdar9 dtc destination address register 9 xxxxh 06c8fh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 50 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.16 sfr information (16) (1) address symbol register name after reset remarks 06c90h dtccr10 dtc control register 10 xxh 06c91h dtbls10 dtc block size register 10 xxh 06c92h dtcct10 dtc transfer count register 10 xxh 06c93h dtrld10 dtc transfer count reload register 10 xxh 06c94h dtsar10 dtc source address register 10 xxxxh 06c95h 06c96h dtdar10 dtc destination address register 10 xxxxh 06c97h 06c98h dtccr11 dtc control register 11 xxh 06c99h dtbls11 dtc block size register 11 xxh 06c9ah dtcct11 dtc transfer count register 11 xxh 06c9bh dtrld11 dtc transfer count reload register 11 xxh 06c9ch dtsar11 dtc source address register 11 xxxxh 06c9dh 06c9eh dtdar11 dtc destination address register 11 xxxxh 06c9fh 06ca0h dtccr12 dtc control register 12 xxh 06ca1h dtbls12 dtc block size register 12 xxh 06ca2h dtcct12 dtc transfer count register 12 xxh 06ca3h dtrld12 dtc transfer count reload register 12 xxh 06ca4h dtsar12 dtc source address register 12 xxxxh 06ca5h 06ca6h dtdar12 dtc destination address register 12 xxxxh 06ca7h 06ca8h dtccr13 dtc control register 13 xxh 06ca9h dtbls13 dtc block size register 13 xxh 06caah dtcct13 dtc transfer count register 13 xxh 06cabh dtrld13 dtc transfer count reload register 13 xxh 06cach dtsar13 dtc source address register 13 xxxxh 06cadh 06caeh dtdar13 dtc destination address register 13 xxxxh 06cafh 06cb0h dtccr14 dtc control register 14 xxh 06cb1h dtbls14 dtc block size register 14 xxh 06cb2h dtcct14 dtc transfer count register 14 xxh 06cb3h dtrld14 dtc transfer count reload register 14 xxh 06cb4h dtsar14 dtc source address register 14 xxxxh 06cb5h 06cb6h dtdar14 dtc destination address register 14 xxxxh 06cb7h 06cb8h dtccr15 dtc control register 15 xxh 06cb9h dtbls15 dtc block size register 15 xxh 06cbah dtcct15 dtc transfer count register 15 xxh 06cbbh dtrld15 dtc transfer count reload register 15 xxh 06cbch dtsar15 dtc source address register 15 xxxxh 06cbdh 06cbeh dtdar15 dtc destination address register 15 xxxxh 06cbfh 06cc0h dtccr16 dtc control register 16 xxh 06cc1h dtbls16 dtc block size register 16 xxh 06cc2h dtcct16 dtc transfer count register 16 xxh 06cc3h dtrld16 dtc transfer count reload register 16 xxh 06cc4h dtsar16 dtc source address register 16 xxxxh 06cc5h 06cc6h dtdar16 dtc destination address register 16 xxxxh 06cc7h 06cc8h dtccr17 dtc control register 17 xxh 06cc9h dtbls17 dtc block size register 17 xxh 06ccah dtcct17 dtc transfer count register 17 xxh 06ccbh dtrld17 dtc transfer count reload register 17 xxh 06ccch dtsar17 dtc source address register 17 xxxxh 06ccdh 06cceh dtdar17 dtc destination address register 17 xxxxh 06ccfh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 51 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.17 sfr information (17) (1) address symbol register name after reset remarks 06cd0h dtccr18 dtc control register 18 xxh 06cd1h dtbls18 dtc block size register 18 xxh 06cd2h dtcct18 dtc transfer count register 18 xxh 06cd3h dtrld18 dtc transfer count reload register 18 xxh 06cd4h dtsar18 dtc source address register 18 xxxxh 06cd5h 06cd6h dtdar18 dtc destination address register 18 xxxxh 06cd7h 06cd8h dtccr19 dtc control register 19 xxh 06cd9h dtbls19 dtc block size register 19 xxh 06cdah dtcct19 dtc transfer count register 19 xxh 06cdbh dtrld19 dtc transfer count reload register 19 xxh 06cdch dtsar19 dtc source address register 19 xxxxh 06cddh 06cdeh dtdar19 dtc destination address register 19 xxxxh 06cdfh 06ce0h dtccr20 dtc control register 20 xxh 06ce1h dtbls20 dtc block size register 20 xxh 06ce2h dtcct20 dtc transfer count register 20 xxh 06ce3h dtrld20 dtc transfer count reload register 20 xxh 06ce4h dtsar20 dtc source address register 20 xxxxh 06ce5h 06ce6h dtdar20 dtc destination address register 20 xxxxh 06ce7h 06ce8h dtccr21 dtc control register 21 xxh 06ce9h dtbls21 dtc block size register 21 xxh 06ceah dtcct21 dtc transfer count register 21 xxh 06cebh dtrld21 dtc transfer count reload register 21 xxh 06cech dtsar21 dtc source address register 21 xxxxh 06cedh 06ceeh dtdar21 dtc destination address register 21 xxxxh 06cefh 06cf0h dtccr22 dtc control register 22 xxh 06cf1h dtbls22 dtc block size register 22 xxh 06cf2h dtcct22 dtc transfer count register 22 xxh 06cf3h dtrld22 dtc transfer count reload register 22 xxh 06cf4h dtsar22 dtc source address register 22 xxxxh 06cf5h 06cf6h dtdar22 dtc destination address register 22 xxxxh 06cf7h 06cf8h dtccr23 dtc control register 23 xxh 06cf9h dtbls23 dtc block size register 23 xxh 06cfah dtcct23 dtc transfer count register 23 xxh 06cfbh dtrld23 dtc transfer count reload register 23 xxh 06cfch dtsar23 dtc source address register 23 xxxxh 06cfdh 06cfeh dtdar23 dtc destination address register 23 xxxxh 06cffh 06d00h to 06dffh 06e00h cmb0_0 can_0 mailbox 0 xxh 06e01h xxh 06e02h xxh 06e03h xxh 06e04h xxh 06e05h xxh 06e06h xxh 06e07h xxh 06e08h xxh 06e09h xxh 06e0ah xxh 06e0bh xxh 06e0ch xxh 06e0dh xxh 06e0eh xxh 06e0fh xxh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 52 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.18 sfr information (18) (1) address symbol register name after reset remarks 06e10h cmb1_0 can_0 mailbox 1 xxh 06e11h xxh 06e12h xxh 06e13h xxh 06e14h xxh 06e15h xxh 06e16h xxh 06e17h xxh 06e18h xxh 06e19h xxh 06e1ah xxh 06e1bh xxh 06e1ch xxh 06e1dh xxh 06e1eh xxh 06e1fh xxh 06e20h cmb2_0 can_0 mailbox 2 xxh 06e21h xxh 06e22h xxh 06e23h xxh 06e24h xxh 06e25h xxh 06e26h xxh 06e27h xxh 06e28h xxh 06e29h xxh 06e2ah xxh 06e2bh xxh 06e2ch xxh 06e2dh xxh 06e2eh xxh 06e2fh xxh 06e30h cmb3_0 can_0 mailbox 3 xxh 06e31h xxh 06e32h xxh 06e33h xxh 06e34h xxh 06e35h xxh 06e36h xxh 06e37h xxh 06e38h xxh 06e39h xxh 06e3ah xxh 06e3bh xxh 06e3ch xxh 06e3dh xxh 06e3eh xxh 06e3fh xxh 06e40h cmb4_0 can_0 mailbox 4 xxh 06e41h xxh 06e42h xxh 06e43h xxh 06e44h xxh 06e45h xxh 06e 46h xxh 06e47h xxh 06e48h xxh 06e49h xxh 06 e 4ah xxh 06e4bh xxh 06e4ch xxh 06e4dh xxh 06e4eh xxh 06e4fh xxh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 53 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.19 sfr information (19) (1) address symbol register name after reset remarks 06e50h cmb5_0 can_0 mailbox 5 xxh 06e51h xxh 06e52h xxh 06e53h xxh 06e54h xxh 06e55h xxh 06e56h xxh 06e57h xxh 06e58h xxh 06e59h xxh 06e5ah xxh 06e5bh xxh 06e5ch xxh 06e5dh xxh 06e5eh xxh 06e5fh xxh 06e60h cmb6_0 can_0 mailbox 6 xxh 06e61h xxh 06e62h xxh 06e63h xxh 06e64h xxh 06e65h xxh 06e66h xxh 06e67h xxh 06e68h xxh 06e69h xxh 06e6ah xxh 06e6bh xxh 06e6ch xxh 06e6dh xxh 06e6eh xxh 06e6fh xxh 06e70h cmb7_0 can_0 mailbox 7 xxh 06e71h xxh 06e72h xxh 06e73h xxh 06e74h xxh 06e75h xxh 06e76h xxh 06e77h xxh 06e78h xxh 06e79h xxh 06e7ah xxh 06e7bh xxh 06e7ch xxh 06e7dh xxh 06e7eh xxh 06e7fh xxh 06e80h cmb8_0 can_0 mailbox 8 xxh 06e81h xxh 06e82h xxh 06e83h xxh 06e84h xxh 06e85h xxh 06e86h xxh 06e 87h xxh 06e88h xxh 06e89h xxh 06e 8 ah xxh 06e8bh xxh 06e8ch xxh 06e8dh xxh 06e8eh xxh 06e8fh xxh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 54 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.20 sfr information (20) (1) address symbol register name after reset remarks 06e90h cmb9_0 can_0 mailbox 9 xxh 06e91h xxh 06e92h xxh 06e93h xxh 06e94h xxh 06e95h xxh 06e96h xxh 06e97h xxh 06e98h xxh 06e99h xxh 06e9ah xxh 06e9bh xxh 06e9ch xxh 06e9dh xxh 06e9eh xxh 06e9fh xxh 06ea0h cmb10_0 can_0 mailbox 10 xxh 06ea1h xxh 06ea2h xxh 06ea3h xxh 06ea4h xxh 06ea5h xxh 06ea6h xxh 06ea7h xxh 06ea8h xxh 06ea9h xxh 06eaah xxh 06eabh xxh 06each xxh 06eadh xxh 06eaeh xxh 06eafh xxh 06eb0h cmb11_0 can_0 mailbox 11 xxh 06eb1h xxh 06eb2h xxh 06eb3h xxh 06eb4h xxh 06eb5h xxh 06eb6h xxh 06eb7h xxh 06eb8h xxh 06eb9h xxh 06ebah xxh 06ebbh xxh 06ebch xxh 06ebdh xxh 06ebeh xxh 06ebfh xxh 06ec0h cmb12_0 can_0 mailbox 12 xxh 06ec1h xxh 06ec2h xxh 06ec3h xxh 06ec4h xxh 06ec5h xxh 06ec6h xxh 06ec7 h xxh 06ec8h xxh 06ec9h xxh 06ecah xxh 06 ecbh xxh 0 6ecch xxh 06ecdh xxh 06eceh xxh 06ecfh xxh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 55 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.21 sfr information (21) (1) address symbol register name after reset remarks 06ed0h cmb13_0 can_0 mailbox 13 xxh 06ed1h xxh 06ed2h xxh 06ed3h xxh 06ed4h xxh 06ed5h xxh 06ed6h xxh 06ed7h xxh 06ed8h xxh 06ed9h xxh 06edah xxh 06edbh xxh 06edch xxh 06eddh xxh 06edeh xxh 06edfh xxh 06ee0h cmb14_0 can_0 mailbox 14 xxh 06ee1h xxh 06ee2h xxh 06ee3h xxh 06ee4h xxh 06ee5h xxh 06ee6h xxh 06ee7h xxh 06ee8h xxh 06ee9h xxh 06eeah xxh 06eebh xxh 06eech xxh 06eedh xxh 06eeeh xxh 06eefh xxh 06ef0h cmb15_0 can_0 mailbox 15 xxh 06ef1h xxh 06ef2h xxh 06ef3h xxh 06ef4h xxh 06ef5h xxh 06ef6h xxh 06ef7h xxh 06ef8h xxh 06ef9h xxh 06efah xxh 06efbh xxh 06efch xxh 06efdh xxh 06efeh xxh 06effh xxh 06f00h 06f01h 06f02h 06f03h 06f04h 06f05h 06f06h 06f07h 06f08h 06f09h 06f0ah 06f0bh 06f0ch 06f0dh 06f0eh 06f0fh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 56 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.22 sfr information (22) (1) address symbol register name after reset remarks 06f10h cmkr0_0 can_0 mask register 0 xxh 06f11h xxh 06f12h xxh 06f13h xxh 06f14h cmkr1_0 can_0 mask register 1 xxh 06f15h xxh 06f16h xxh 06f17h xxh 06f18h cmkr2_0 can_0 mask register 2 xxh 06f19h xxh 06f1ah xxh 06f1bh xxh 06f1ch cmkr3_0 can_0 mask register 3 xxh 06f1dh xxh 06f1eh xxh 06f1fh xxh 06f20h cfidcr0_0 can_0 fifo received id compare register 0 xxh 06f21h xxh 06f22h xxh 06f23h xxh 06f24h cfidcr1_0 can_0 fifo received id compare register 1 xxh 06f25h xxh 06f26h xxh 06f27h xxh 06f28h 06f29h 06f2ah cmkivlr_0 can_0 mask invalid register xxh 06f2bh xxh 06f2ch 06f2dh 06f2eh cmier_0 can_0 mailbox interrupt enable register xxh 06f2fh xxh 06f30h cmctl0_0 can_0 message control register 0 00h 06f31h cmctl1_0 can_0 message control register 1 00h 06f32h cmctl2_0 can_0 message control register 2 00h 06f33h cmctl3_0 can_0 message control register 3 00h 06f34h cmctl4_0 can_0 message control register 4 00h 06f35h cmctl5_0 can_0 message control register 5 00h 06f36h cmctl6_0 can_0 message control register 6 00h 06f37h cmctl7_0 can_0 message control register 7 00h 06f38h cmctl8_0 can_0 message control register 8 00h 06f39h cmctl9_0 can_0 message control register 9 00h 06f3ah cmctl10_0 can_0 message control register 10 00h 06f3bh cmctl11_0 can_0 message control register 11 00h 06f3ch cmctl12_0 can_0 message control register 12 00h 06f3dh cmctl13_0 can_0 message control register 13 00h 06f3eh cmctl14_0 can_0 message control register 14 00h 06f3fh cmctl15_0 can_0 message control register 15 00h 06f40h cctlr_0 can_0 control register 00000101b 06f41h 00h 06f42h cstr_0 can_0 status register 00000101b 06f43h 00h 06f44h cbcr_0 can_0 bit configuration register 00h 06f45h 00h 06f46h 00h 06f47h cclkr_0 can_0 clock select register 00h 06f48h crfcr_0 can_0 receive fifo control register 10000000b 06f49h crfpcr_0 can_0 receive fifo pointer control register xxh 06f4ah ctfcr_0 can_0 transmit fifo control register 10000000b 06f4bh ctfpcr_0 can_0 transmit fifo pointer control register xxh 06f4ch ceier_0 can_0 error interrupt enable register 00h 06f4dh ceifr_0 can_0 error interrupt factor judge register 00h 06f4eh crecr_0 can_0 receive error count register 00h 06f4fh ctecr_0 can_0 transmit error count register 00h
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 57 of 85 sep 05, 2012 x: undefined note: 1. the blank areas are reserved. no access is allowed. table 3.23 sfr information (23) (1) address symbol register name after reset remarks 06f50h cecsr_0 can_0 error code store register 00h 06f51h ccssr_0 can_0 channel search support register xxh 06f52h cmssr_0 can_0 mailbox search status register 10000000b 06f53h cmsmr_0 can_0 mailbox search mode register 00h 06f54h ctsr_0 can_0 time stamp register 0000h 06f55h 06f56h cafsr_0 can_0 acceptance filter support register xxh 06f57h xxh 06f58h ctcr_0 can_0 test control register 00h 06f59h 06f5ah 06f5bh 06f5ch 06f5dh 06f5eh 06f5fh 06f60h 06f61h 06f62h 06f63h 06f64h 06f65h 06f66h 06f67h 06f68h 06f69h 06f6ah 06f6bh 06f6ch 06f6dh 06f6eh 06f6fh 06f70h 06f71h 06f72h 06f73h 06f74h 06f75h 06f76h 06f77h 06f78h 06f79h 06f7ah 06f7bh 06f7ch 06f7dh 06f7eh canisr_0 can_0 interrupt status register 00h 06f7fh canie_0 can_0 interrupt control register 00h 06f80h to 06fffh
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 3. address space r01ds0042ej0200 rev.2.00 page 58 of 85 sep 05, 2012 notes: 1. the option function select area is allocated in the flash memory , not in the sfrs. set appropriate values as rom data by a pr ogram. do not perform any additional writes to the option function select area. erasing the block including the option function select area sets the option function select area to ffh. 2. the id code area is allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not p erform any additional writes to the id code area. erasing the block in cluding the id code area sets the id code area to ffh. table 3.24 id code area, option function select area address symbol area name after reset address size : 0ffdbh ofs2 option function select register 2 (note 1) : 0ffdfh id1 (note 2) : 0ffe3h id2 (note 2) : 0ffebh id3 (note 2) : 0ffefh id4 (note 2) : 0fff3h id5 (note 2) : 0fff7h id6 (note 2) : 0fffbh id7 (note 2) : 0ffffh ofs option function select register (note 1)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 59 of 84 sep 05, 2012 4. electrical characteristics 4.1 absolute maximum ratings notes: 1. meet the specified range for the input voltage or the input current. 2. applicable ports: p0 to p3, p4_3 to p4_5, p5_0 to p5_4, p5_6, p5_7, p6, and p8_0 to p8_6. 3. the total input current must be 12 ma or less. 4. the input current may cause the mcu to be powered on and operate even if no voltage is supplied to vcc. when a voltage is supplied to vcc, the input current may cause the supply voltage to rise. since operations in any cases other than above are not guarante ed, use the power supply circuit in the system to ensure the supply voltage for the mcu is stable within the specified range. table 4.1 absolute maximum ratings symbol parameter condition rated value unit vcc/avcc supply voltage ? 0.3 to 6.5 v v i input voltage (1) ? 0.3 to vcc + 0.3 v iin input current (1) (2, 3, 4) ? 4 to 4 ma v o output voltage ? 0.3 to vcc + 0.3 v p d power dissipation ? 40c ? topr ? 85c 300 mw 85c ? to p r ? 125c 125 mw t opr operating ambient temperature ? 40 to 85 (j version)/ ? 40 to 125 (k version) c t stg storage temperature ? 65 to 150 c
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 60 of 84 sep 05, 2012 4.2 recommended operating conditions note: 1. the average output current indicates the average value of current measured during 100 ms. table 4.2 recommended operating conditions (1) (vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.7 D 5.5 v v ss /av ss supply voltage D 0 D v v ih input high voltage other than cmos input 0.8 v cc D v cc v cmos input input level switching function (i/o port) input level selection : 0.35v cc 4.0 v ? v cc ? 5.5 v 0.5 v cc D v cc v 2.7 v ? v cc ? 4.0 v 0.55 v cc D v cc v input level selection : 0.5v cc 4.0 v ? v cc ? 5.5 v 0.65 v cc D v cc v 2.7 v ? v cc ? 4.0 v 0.7 v cc D v cc v input level selection : 0.7v cc 4.0 v ? v cc ? 5.5 v 0.85 v cc D v cc v 2.7 v ? v cc ? 4.0 v 0.85 v cc D v cc v external clock input (xout) 1.2 D v cc v v il input low voltage other than cmos input 0 D 0.2 v cc v cmos input input level switching function (i/o port) input level selection : 0.35v cc 4.0 v ? v cc ? 5.5 v 0 D 0.2 v cc v 2.7 v ? v cc ? 4.0 v 0 D 0.2 v cc v input level selection : 0.5v cc 4.0 v ? v cc ? 5.5 v 0 D 0.4 v cc v 2.7 v ? v cc ? 4.0 v 0 D 0.3 v cc v input level selection : 0.7v cc 4.0 v ? v cc ? 5.5 v 0 D 0.55 v cc v 2.7 v ? v cc ? 4.0 v 0 D 0.45 v cc v external clock input (xout) 0 D 0.4 v i oh(sum) peak sum output high current sum of all pins i oh(peak) DD ? 80 ma i oh(sum) average sum output high current sum of all pins i oh(avg) DD ? 40 ma i oh(peak) peak output high current when drive capacity is low DD ? 10 ma when drive capacity is high DD ? 40 ma i oh(avg) average output high current when drive capacity is low DD ? 5ma when drive capacity is high DD ? 20 ma i ol(sum) peak sum output low current sum of all pins i ol(peak) DD 80 ma i ol(sum) average sum output low current sum of all pins i ol(avg) DD 40 ma i ol(peak) peak output low current when drive capacity is low DD 10 ma when drive capacity is high DD 40 ma i ol(avg) average output low current when drive capacity is low DD 5ma when drive capacity is high DD 20 ma f (xin) xin clock input oscillation frequency 2.7 v ? v cc ? 5.5 v DD 20 mhz f (pll) pll clock frequency 2.7 v ? v cc ? 5.5 v 10 D 32 mhz fhoco count source for timer rc and timer rd 2.7 v ? v cc ? 5.5 v 32 D 40 mhz fhoco-f fhoco-f frequency 2.7 v ? v cc ? 5.5 v DD 20 mhz ? system clock frequency 2.7 v ? v cc ? 5.5 v DD 32 mhz f (bclk) cpu clock frequency 2.7 v ? v cc ? 5.5 v DD 32 mhz t su(pll) pll frequency synthesizer stabilization wait time 2.7 v ? v cc ? 5.5 v DD 1ms
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 61 of 84 sep 05, 2012 figure 4.1 timing measurement circuit for ports p0 to p3, p4_3 to p4_7, p5_0 to p5_4, p5_6, p5_7, p6, p8_0 to p8_6, p9_4 to p9_7, and pc_0 to pc_4 note: 1. the power supply ripple must meet either or both v r(vcc) and dv r(vcc)/dt figure 4.2 power supply ripple waveform table 4.3 recommended operating conditions (2) (vcc = 4.5 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. iic(h) input high injection current p0, p1, p2, p3, p4_3 to p4_5, p5_0 to p5_4, p5_6, p5_7, p6, p8_0 to p8_6 v i ? v cc DD 2ma iic(l) input low injection current p0, p1, p2, p3, p4_3 to p4_5, p5_0 to p5_4, p5_6, p5_7, p6, p8_0 to p8_6 v i ? v ss DD ? 2ma ? [iic] total injection current DD 8ma table 4.4 recommended operating conditions (3) (vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. v r(vcc) allowable power supply ripple voltage (1) DD 0.1v cc v dv r(vcc)/dt power supply ripple falling gradient (1) DD 10 v/ms 30 pf p0, p1, p2, p3 p4_3 to p4_7 p5_0 to p5_4 p5_6, p5_7 p6 p8_0 to p8_6 p9_4 to p9_7 pc_0 to pc_4 v r(vcc) v cc
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 62 of 84 sep 05, 2012 4.3 peripheral function characteristics notes: 1. if the cpu and the flash memory stop, t he a/d conversion result will be undefined. 2. when the analog input voltage exceeds the reference voltage, t he a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. table 4.5 a/d converter characteristics (vcc/avcc = vref = 2.7 v to 5.5 v, vss = 0 v, topr = ? 40c to 85c(j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. D resolution v ref = avcc DD 10 bit D absolute accuracy 10-bit mode v ref = avcc = 5.0 v an0 to an11 input anex0 to anex3 input DD 3 lsb v ref = avcc = 3.3 v an0 to an11 input anex0 to anex3 input DD 5 lsb v ref = avcc = 3.0 v an0 to an11 input anex0 to anex3 input DD 5 lsb 8-bit mode v ref = avcc = 5.0 v an0 to an11 input anex0 to anex3 input DD 2 lsb v ref = avcc = 3.3 v an0 to an11 input anex0 to anex3 input DD 2 lsb v ref = avcc = 3.0 v an0 to an11 input anex0 to anex3 input DD 2 lsb ? ad a/d conversion clock 4.0 v ? v ref = avcc ? 5.5 v (1) 2 D 20 mhz 3.2 v ? v ref = avcc ? 5.5 v (1) 2 D 16 mhz 2.7 v ? v ref = avcc ? 5.5 v (1) 2 D 10 mhz D tolerance level impedance D 3 D k ? i vref vref current vcc = 5 v, xin = f1 = fad = 20 mhz D 45 D a t conv conversion time 10-bit mode v ref = avcc = 5.0 v, ? ad = 20 mhz 2.2 DD s 8-bit mode v ref = avcc = 5.0 v, ? ad = 20 mhz 2.2 DD s t samp sampling time ? ad = 20 mhz 0.8 DD s v ref reference voltage 2.7 D avcc v v ia analog input voltage (2) 0 D v ref v ocvref on-chip reference voltage 2mhz ? ? ad ? 4mhz 1.14 1.34 1.54 v
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 63 of 84 sep 05, 2012 note: 1. when the digital filter is not selected. table 4.6 comparator b characteristics (vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. v ref ivref1, ivref3 input reference voltage 0 D vcc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 D vcc + 0.3 v D offset D 5 100 mv t d comparator output delay time (1) v i = v ref 100 mv D 0.1 D s i cmp comparator operating current vcc = 5.0 v D 17.5 D a
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 64 of 84 sep 05, 2012 notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. for example, if 1,024 1- byte writes are performed to different addresses in bloc k a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure c ount can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. the data hold time includes 3,000 hours under an environment of ambient temperature 125c and 7,000 hours under an environment of ambient temperature 85c. table 4.7 flash memory (program rom) characteristics (vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. D program/erase endurance (1) mcu with data flash 1,000 (2) DD times mcu without data flash 100 (2) DD times D byte program time (program and erase endurance ? 100 times) DD D s D byte program time (program and erase endurance ? 1,000 times) DD D s D word program time (program and erase endurance ? 100 times) topr = 25c, v cc = 5.0 v D 100 200 s D word program time (program and erase endurance ? 100 times) D 100 400 s D word program time (program and erase endurance ? 1,000 times) D 100 650 s D block erase time D 0.3 4 s t d(sr-sus) time delay from suspend request until suspend DD 5 + cpu clock 3 cycles ms D interval from erase start/restart until following suspend request 0 DD s D time from suspend until erase restart DD 30 + cpu clock 1 cycle s t d(cmdrst -ready) time from when command is forcibly terminated until reading is enabled DD 30 + cpu clock 1 cycle s D program, erase voltage 2.7 D 5.5 v D read voltage 2.7 D 5.5 v D program, erase temperature ? 40 D 85 (j version) 125 (k version) c D data hold time ambient temperature = 55c (6) 20 DD year
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 65 of 84 sep 05, 2012 notes: 1. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100, 1,000 or 10,000), each block can be eras ed n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 2. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 3. in a system that executes multiple programming operations, the actual erasure c ount can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. in addition, averaging the erasure endurance between blocks a to d can further reduce the actual erasure endurance. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 4. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 5. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 6. the data hold time includes 3,000 hours under an environment of ambient temperature 125c and 7,000 hours under an environment of ambient temperature 85c. table 4.8 flash memory (data flash block a to block d) characteristics (vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard unit min. typ. max. D program/erase endurance (1) 10,000 (2) DD times D byte program time (program and erase endurance ? 1,000 times) D 160 950 s D byte program time (program and erase endurance > 1,000 times) D 300 950 s D block erase time (program and erase endurance ? 1,000 times) D 0.2 1 s D block erase time (program and erase endurance > 1,000 times) D 0.3 1 s t d(sr-sus) time delay from suspend request until suspend DD 3 + cpu clock 3 cycles ms D interval from erase start/restart until following suspend request 0 DD s D time from suspend until erase restart DD 30 + cpu clock 1 cycle s t d(cmdrst -ready) time from when command is forcibly terminated until reading is enabled DD 30 + cpu clock 1 cycle s D program, erase voltage 2.7 D 5.5 v D read voltage 2.7 D 5.5 v D program, erase temperature ? 40 D 85 (j ver.) 125 (k ver.) c D data hold time ambient temperature = 55c (6) 20 DD year
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 66 of 84 sep 05, 2012 figure 4.3 time delay from suspend request until suspend notes: 1. the voltage detection level must be selected with bits vdsel0 and vdsel1 in the ofs register. 2. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. table 4.9 voltage detection 0 circuit characteristics (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. v det0 voltage detection level vdet0_2 (1) when vcc falls 2.70 2.85 3.05 v voltage detection level vdet0_3 (1) when vcc falls 3.55 3.80 4.05 v D voltage detection 0 ci rcuit response time (2) at the falling of vcc from 5 v to (vdet0 ? 0.1) v D 6 150 s D voltage detection circuit self power consumption vca25 = 1, vcc = 5.0 v D 1.5 D a t d(e-a) waiting time until voltage detection circuit operation starts (3) DD 100 s fst6 bit suspend request (fmr21 bit) fixed time clock-dependent time access restart fst6: bit in fst register fmr21: bit in fmr2 register t d(sr-sus)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 67 of 84 sep 05, 2012 notes: 1. select the voltage detection level with bi ts vd1s0 to vd1s3 in the vd1ls register. 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. notes: 1. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 4.10 voltage detection 1 circuit characteristics (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. v det1 voltage detection level vdet1_7 (1) when vcc falls 2.95 3.25 3.55 v voltage detection level vdet1_8 (1) when vcc falls 3.10 3.40 3.70 v voltage detection level vdet1_9 (1) when vcc falls 3.25 3.55 3.85 v voltage detection level vdet1_a (1) when vcc falls 3.40 3.70 4.00 v voltage detection level vdet1_b (1) when vcc falls 3.55 3.85 4.15 v voltage detection level vdet1_c (1) when vcc falls 3.70 4.00 4.30 v voltage detection level vdet1_d (1) when vcc falls 3.85 4.15 4.45 v voltage detection level vdet1_e (1) when vcc falls 4.00 4.30 4.60 v voltage detection level vdet1_f (1) when vcc falls 4.15 4.45 4.75 v D hysteresis width at the rising of vcc in voltage detection 1 circuit D 0.10 D v D voltage detection 1 ci rcuit response time (2) at the falling of vcc from 5 v to (vdet1 ? 0.1) v D 60 150 s D voltage detection circuit self power consumption vca26 = 1, vcc = 5.0 v D 1.7 D a t d(e-a) waiting time until voltage detection circuit operation starts (3) DD 100 s table 4.11 voltage detection 2 circuit characteristics (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. v det2 voltage detection level vdet2_0 when vcc falls 3.70 4.00 4.30 v D hysteresis width at the rising of vcc in voltage detection 2 circuit D 0.1 D s D voltage detection 2 circ uit response time (1) at the falling of vcc from 5 v to (vdet2_0 ? 0.1) v D 20 150 s D voltage detection circ uit self power consumption vca27 = 1, vcc = 5.0 v D 1.7 D a t d(e-a) waiting time until voltage detection circuit operation starts (2) DD 100 s
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 68 of 84 sep 05, 2012 note: 1. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 4.4 power-on reset circuit characteristics notes: 1. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. 2. this indicates the precision error for the oscillation frequency of the high-speed on-chip oscillator. table 4.12 power-on reset circuit characteristics (1) (measurement conditions: topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. t rth external power vcc rise gradient 0 D 50,000 mv/msec table 4.13 high-speed on-chip oscillator circuit characteristics symbol parameter conditions standard unit min. typ. max. D high-speed on-chip oscillator frequency after reset vcc = 2.7 v to 5.5 v, ? 40c ?? topr ? 85c (j version) ? 40c ??? to p r ??? 125c (k version) D 40 D mhz high-speed on-chip oscillator frequency when 01b is written to bits fra25 and fra24 in the fra2 register (1) ? 36.864 ? mhz high-speed on-chip oscillator frequency when 10b is written to bits fra25 and fra24 in the fra2 register ?32?mhz high-speed on-chip oscillator frequency temperature and power supply voltage dependency (2) ? 1.5 D 1.5 % D oscillation stabili ty time vcc = 5.0 v, topr = 25c D 250 D s D self power consumption at oscill ation vcc = 5.0 v, topr = 25c D 400 D a notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. refer to the voltage detection circuit chapter of users manual : hardware for details. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 rese t disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) 1 f loco-s ? 32 1 f loco-s ? 32 external power v cc t rth t rth
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 69 of 84 sep 05, 2012 note: 1. waiting time until the internal power su pply generation circuit stabilizes during power-on. table 4.14 low-speed on-chip oscillator circuit characteristics (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. floco low-speed on-chip oscillator frequency 2.7 v ? vcc ? 4.2 v 106.25 125 143.75 khz 4.2 v ? vcc ? 5.5 v 112.5 125 137.5 khz flocowdt low-speed on-chip oscillator frequency for the watchdog timer 2.7 v ? vcc ? 4.2 v 106.25 125 143.75 khz 4.2 v ? vcc ? 5.5 v 112.5 125 137.5 khz D oscillation stability time vcc = 5.0 v, topr = 25c D 30 100 s D self power consumption at oscillation vcc = 5.0 v, topr = 25c D 3 D a table 4.15 power supply circuit characteristics (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (1) DD 2,000 s
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 70 of 84 sep 05, 2012 4.4 dc characteristics table 4.16 dc characteristics (1) [4.2 v ? vcc ? 5.5 v] (vcc = 4.2 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), f (xin) = 20 mhz, unless otherwise specified) symbol parameter conditions standard unit min. typ. max. v oh output high voltage other than xout drive capacity is high i oh = ? 20 ma vcc ? 2.0 D vcc v drive capacity is low i oh = ? 5 ma vcc ? 2.0 ? vcc v i oh = ? 200 ? avcc ? 0.3 ? vcc v xout i oh = ? 200 ? a1 . 0?v c cv v ol output low voltage other than xout drive capacity is high i ol = 20 ma DD 2.0 v drive capacity is low i ol = 5 ma ? ? 2.0 v i ol = 200 ? a??0 . 4 5v xout i ol = 200 ? a??0 . 5v v t+- v t- hysteresis int0 to int 4 , ki0 to ki3 , trjio_0, trjio_1, trcclk_0, trcclk_1, trctrg_0, trctrg_1, trcioa_0, trciob_0, trcioc_0, trciod_0, trcioa_1, trciob_1, trcioc_1, trciod_1, trdioa0_0, trdioa1_0, trdiob0_0, trdiob1_0, trdioc0_0, trdioc1_0, trdiod0_0, trdiod1_0, trdclk_0, trfi, trgioa, trgiob, trgclka, trgclkb, clk_0, clk_1, rxd_0, rxd_1, cts2 , rxd2, scl_0, scl_1, sda_0, sda_1, ssi_0, ssi_1, scs_0 , scs_1 , ssck_0, ssck_1, sso_0, sso_1 vcc = 5.0 v 0.1 1.2 D v reset vcc = 5.0 v 0.1 1.2 D v i ih input high current v i = 5.0 v, vcc = 5.0 v DD 1.0 a i il input low current v i = 0 v, vcc = 5.0 v DD ? 1.0 a r pullup pull-up resistance v i = 0 v, vcc = 5.0 v 25 50 100 k ? r fxin feedback resistance xin D 0.3 D m ? v ram ram hold voltage during stop mode 2.0 DD v
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 71 of 84 sep 05, 2012 notes: 1. vcc = 3.3 v to 5.5 v, single-chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. fhoco-f 4. the typical value (typ.) indicates the curr ent value when the cpu and the memory operate. the maximum value (max.) indicates the current value when the cpu, the memory, and the peripheral functions operate and the flash memory is programmed/erased. table 4.17 dc characteristics (2) [3.3 v ? vcc ? 5.5 v] (topr = ? 40c to 85c (j version) , unless otherwise specified) symbol parameter conditions standard (4) unit oscillation on-chip oscillator multiplication, division cpu clock low-power- consumption setting other min. typ. max. xin (2) high- speed low- speed i cc power supply current (1) pll operating mode 4 mhz off 125 khz multiply-by-8 32 mhz DD 14.0 21 ma high-speed clock mode 20 mhz off 125 khz no division 20 mhz DD 8.2 16.4 ma 16 mhz off 125 khz no division 16 mhz DD 6.7 13.4 ma 10 mhz off 125 khz no division 10 mhz DD 4.4 D ma 20 mhz off 125 khz multiply-by-8 2.5 mhz DD 3.6 D ma 16 mhz off 125 khz multiply-by-8 2 mhz DD 2.9 D ma 10 mhz off 125 khz multiply-by-8 1.25 mhz DD 2.0 D ma high-speed on- chip oscillator mode off 20 mhz (3) 125 khz no division 20 mhz DD 8.7 17.4 ma off 20 mhz (3) 125 khz divide-by-8 2.5 mhz DD 4.1 D ma off 4 mhz (3) 125 khz divide-by-16 250 mhz mstiic = 1 msttrd = 1 msttrc = 1 D 1.4 D ma low-speed on- chip oscillator mode off off 125 khz divide-by-8 15.625 mhz fmr27 = 1 svc0 = 0 D 100 200 a wait mode off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock operation D 15 120 a off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock off D 5110 a stop mode off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 to p r = 2 5 c peripheral clock off D 2.5 5.0 a off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 to p r = 8 5 c peripheral clock off D 30.0 D a
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 72 of 84 sep 05, 2012 notes: 1. vcc = 3.3 v to 5.5 v, single-chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. fhoco-f 4. the typical value (typ.) indicates the curr ent value when the cpu and the memory operate. the maximum value (max.) indicates the current value when the cpu, the memory, and the peripheral functions operate and the flash memory is programmed/erased. table 4.18 dc characteristics (3) [3.3 v ? vcc ? 5.5 v] (topr = ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard (4) unit oscillation on-chip oscillator multiplication, division cpu clock low-power- consumption setting other min. typ. max. xin (2) high- speed low- speed i cc power supply current (1) pll operating mode 4 mhz off 125 khz multiply-by-8 32 mhz DD 14.0 21 ma high-speed clock mode 20 mhz off 125 khz no division 20 mhz DD 8.2 16.4 ma 16 mhz off 125 khz no division 16 mhz DD 6.7 13.4 ma 10 mhz off 125 khz no division 10 mhz DD 4.4 D ma 20 mhz off 125 khz multiply-by-8 2.5 mhz DD 3.6 D ma 16 mhz off 125 khz multiply-by-8 2 mhz DD 2.9 D ma 10 mhz off 125 khz multiply-by-8 1.25 mhz DD 2.0 D ma high-speed on- chip oscillator mode off 20 mhz (3) 125 khz no division 20 mhz DD 8.7 17.4 ma off 20 mhz (3) 125 khz divide-by-8 2.5 mhz DD 4.1 D ma off 4 mhz (3) 125 khz divide-by-16 250 mhz mstiic = 1 msttrd = 1 msttrc = 1 D 1.4 D ma low-speed on- chip oscillator mode off off 125 khz divide-by-8 15.625 mhz fmr27 = 1 svc0 = 0 D 100 400 a wait mode off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock operation D 15 330 a off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock off D 5320 a stop mode off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 to p r = 2 5 c peripheral clock off D 2.5 5.0 a off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 125c peripheral clock off D 120 D a
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 73 of 84 sep 05, 2012 table 4.19 dc characteristics (4) [2.7 v ? vcc ? 4.2 v] (measurement conditions: 2.7 v ? vcc ? 4.2 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version), f (xin) = 10 mhz)) symbol parameter conditions standard unit min. typ. max. v oh output high voltage other than xout drive capacity is high i oh = ? 5 ma vcc ? 0.5 D vcc v drive capacity is low i oh = ? 1 ma vcc ? 0.5 ? vcc v xout i oh = ? 200 ? a1 . 0?v c cv v ol output low voltage other than xout drive capacity is high i ol = 5 ma DD 0.5 v drive capacity is low i ol = 1 ma ? ? 0.5 v xout i ol = 200 ? a??0 . 5v v t+- v t- hysteresis int0 to int 4 , ki0 to ki3 , trjio_0, trjio_1, trcclk_0, trcclk_1, trctrg_0, trctrg_1, trcioa_0, trciob_0, trcioc_0, trciod_0, trcioa_1, trciob_1, trcioc_1, trciod_1, trdioa0_0, trdioa1_0, trdiob0_0, trdiob1_0, trdioc0_0, trdioc1_0, trdiod0_0, trdiod1_0, trdclk_0, trfi, trgioa, trgiob, trgclka, trgclkb, clk_0, clk_1, rxd_0, rxd_1, cts2 , rxd2, scl_0, scl_1, sda_0, sda_1, ssi_0, ssi_1 scs_0 , scs_1 , ssck_0, ssck_1, sso_0, sso_1 0.1 0.4 D v reset vcc = 3.0 v 0.1 0.5 D v i ih input high current v i = 3.0 v, vcc = 3.0 v DD 1.0 a i il input low current v i = 0 v, vcc = 3.0 v DD ? 1.0 a r pullup pull-up resistance v i = 0 v, vcc = 3.0 v 42 84 168 k ? r fxin feedback resistance xin D 0.3 D m ? v ram ram hold voltage during stop mode 2.0 DD v
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 74 of 84 sep 05, 2012 notes: 1. vcc = 2.7 v to 3.3 v, single-chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. fhoco-f 4. the typical value (typ.) indicates the curr ent value when the cpu and the memory operate. the maximum value (max.) indicates the current value when the cpu, the memory, and the peripheral functions operate and the flash memory is programmed/erased. table 4.20 dc characteristics (5) [2.7 v ? vcc ? 3.3 v] (topr = ? 40c to 85c (j version) , unless otherwise specified) symbol parameter conditions standard (4) unit oscillation on-chip oscillator multiplication, division cpu clock low-power- consumption setting other min. typ. max. xin (2) high- speed low- speed i cc power supply current (1) pll operating mode 4 mhz off 125 khz multiply-by-8 32 mhz DD 14.0 20.5 ma high-speed clock mode 20 mhz off 125 khz no division 20 mhz DD 8.2 16 ma 16 mhz off 125 khz no division 16 mhz DD 6.7 13 ma 10 mhz off 125 khz no division 10 mhz DD 4.4 D ma 20 mhz off 125 khz multiply-by-8 2.5 mhz DD 3.6 D ma 16 mhz off 125 khz multiply-by-8 2 mhz DD 2.9 D ma 10 mhz off 125 khz multiply-by-8 1.25 mhz DD 2.0 D ma high-speed on- chip oscillator mode off 20 mhz (3) 125 khz no division 20 mhz DD 8.7 17 ma off 20 mhz (3) 125 khz divide-by-8 2.5 mhz DD 4.1 D ma off 4 mhz (3) 125 khz divide-by-16 250 mhz mstiic = 1 msttrd = 1 msttrc = 1 D 1.4 D ma low-speed on- chip oscillator mode off off 125 khz divide-by-8 15.625 mhz fmr27 = 1 svc0 = 0 D 100 200 a wait mode off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock operation D 15 120 a off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock off D 5110 a stop mode off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25c peripheral clock off D 2.5 5.0 a off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 85c peripheral clock off D 30.0 D a
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 75 of 84 sep 05, 2012 notes: 1. vcc = 2.7 v to 3.3 v, single-chip mode, output pins are open, and other pins are vss. 2. xin is set to square wave input. 3. fhoco-f 4. the typical value (typ.) indicates the curr ent value when the cpu and the memory operate. the maximum value (max.) indicates the current value when the cpu, the memory, and the peripheral functions operate and the flash memory is programmed/erased. table 4.21 dc characteristics (6) [2.7 v ? vcc ? 3.3 v] (topr = ? 40c to 125c (k version), unless otherwise specified) symbol parameter conditions standard (4) unit oscillation on-chip oscillator multiplication, division cpu clock low-power- consumption setting other min. typ. max. xin (2) high- speed low- speed i cc power supply current (1) pll operating mode 4 mhz off 125 khz multiply-by-8 32 mhz DD 14.0 20.5 ma high-speed clock mode 20 mhz off 125 khz no division 20 mhz DD 8.2 16 ma 16 mhz off 125 khz no division 16 mhz DD 6.7 13 ma 10 mhz off 125 khz no division 10 mhz DD 4.4 D ma 20 mhz off 125 khz multiply-by-8 2.5 mhz DD 3.6 D ma 16 mhz off 125 khz multiply-by-8 2 mhz DD 2.9 D ma 10 mhz off 125 khz multiply-by-8 1.25 mhz DD 2.0 D ma high-speed on- chip oscillator mode off 20 mhz (3) 125 khz no division 20 mhz DD 8.7 17 ma off 20 mhz (3) 125 khz divide-by-8 2.5 mhz DD 4.1 D ma off 4 mhz (3) 125 khz divide-by-16 250 mhz mstiic = 1 msttrd = 1 msttrc = 1 D 1.4 D ma low-speed on- chip oscillator mode off off 125 khz divide-by-8 15.625 mhz fmr27 = 1 svc0 = 0 D 100 390 a wait mode off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock operation D 22 320 a off off 125 khz DD vca27 = 0 vca26 = 0 vca25 = 0 svc0 = 1 while a wait instruction is executed peripheral clock off D 6310 a stop mode off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 25c peripheral clock off D 2.5 5.0 a off off off DD vca27 = 0 vca26 = 0 vca25 = 0 cm10 = 1 topr = 125c peripheral clock off D 120 D a
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 76 of 84 sep 05, 2012 4.5 ac characteristics note: 1. 1t cyc = 1/f1 (s), f1 ? 20 mhz table 4.22 timing requirements of clock synchronous serial i/o with chip select (during master operation) (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4.00 DD t cyc (1) t hi ssck clock high width 0.40 D 0.60 t sucyc t lo ssck clock low width 0.40 D 0.60 t sucyc t rise ssck clock rising time 2.7 v ? vcc ? 5.5 v DD 0.50 t cyc (1) t fall ssck clock falling time 2.7 v ? vcc ? 5.5 v DD 0.50 t cyc (1) t su ssi, sso data input setup time 4.5 v ? vcc ? 5.5 v 60 DD ns 2.7 v ? vcc ? 4.5 v 70 DD ns t h ssi, sso data input hold time 2.7 v ? vcc ? 5.5 v 2.00 DD t cyc (1) t lead scs -sck output delay time 0.5 t sucyc - 1 t cyc DD ns t lag sck -scs output valid time 0.5 t sucyc - 1 t cyc DD ns t od sso data output delay time 2.7 v ? vcc ? 5.5 v DD 30.00 ns
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 77 of 84 sep 05, 2012 note: 1. 1t cyc = 1/f1 (s), f1 ? 20 mhz table 4.23 timing requirements of clock synchronous serial i/o with chip select (during slave operation) (measurement conditions: vcc = 2.7 v to 5.5 v, topr = ? 40c to 85c (j version)/ ? 40c to 125c (k version)) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4.00 DD t cyc (1) t hi ssck clock high width 0.40 D 0.60 t sucyc t lo ssck clock low width 0.40 D 0.60 t sucyc t rise ssck clock rising time DD 1.00 s t fall ssck clock falling time DD 1.00 s t su sso data input setup time 10.00 DD ns t h sso data input hold time 2.00 DD t cyc (1) t lead scs setup time 1t cyc + 50 DD ns t lag scs hold time 1t cyc + 50 DD ns t od ssi, sso data output delay time 4.5 v ? vcc ? 5.5 v DD 60 ns 2.7 v ? vcc ? 4.5 v DD 70 ns t sa ssi slave access time 2.7 v ? vcc ? 5.5 v DD 1.5t cyc + 100 ns t or ssi slave out open time 2.7 v ? vcc ? 5.5 v DD 1.5t cyc + 100 ns
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 78 of 84 sep 05, 2012 figure 4.5 i/o timing of synchronous serial communication unit (ssu) (master) v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in simr1 register t lead t lag
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 79 of 84 sep 05, 2012 figure 4.6 i/o timing of synchronous serial communication unit (ssu) (slave) v ih or v oh v il or v ol scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v il or v ol t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in simr1 register
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4 . electrical characteristics r01ds0042ej0200 rev.2.00 page 80 of 84 sep 05, 2012 figure 4.7 i/o timing of synchronous serial communication unit (ssu) (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v il or v ol
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4. electr ical characteristics r01ds0042ej0200 rev.2.00 page 81 of 84 sep 05, 2012 note: 1. 1t cyc = 1/f1 (s), f1 ? 20 mhz figure 4.8 i/o timing of i 2 c bus interface table 4.24 timing requirements of i 2 c bus interface (measurement conditions: v cc = 2.7 v to 5.5 v, and topr = ? 40 to 85c (j version)/ ? 40 to 125c (k version)) symbol parameter conditions standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (1) DD ns t sclh scl input high width 3t cyc + 300 (1) DD ns t scll scl input low width 5t cyc + 500 (1) DD ns t sf scl, sda input fall time DD 300 ns t sp scl, sda input spike pulse rejection time DD 1t cyc (1) ns t buf sda input bus-free time 5t cyc (1) DD ns t stah start condition input hold time 3t cyc (1) DD ns t stas repeat start condition input setup time 3t cyc (1) DD ns t stop stop condition input setup time 3t cyc (1) DD ns t sdas data input setup time 1t cyc + 40 (1) DD ns t sdah data input hold time 10 DD ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. repeat start condition
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4. electr ical characteristics r01ds0042ej0200 rev.2.00 page 82 of 84 sep 05, 2012 figure 4.9 external clock input timing diagram figure 4.10 input timing of trjio table 4.25 external clock input (xout) symbol parameter standard unit vcc = 3 v, topr = 25c vcc = 5 v, topr = 25c min. max. min. max. t c(xout) xout input cycle time 50 D 50 D ns t wh(xout) xout input high width 24 D 24 D ns t wl(xout) xout input low width 24 D 24 D ns table 4.26 timing requirements of trjio symbol parameter standard unit vcc = 3v, topr = 25c vcc = 5 v, topr = 25c min. max. min. max. t c(trjio) trjio input cycle time 300 D 100 D ns t wh(trjio) trjio input high width 120 D 40 D ns t wl(trjio) trjio input low width 120 D 40 D ns external clock input t wh(xout) t c(xout) t wl(xout) trjio input t c(trjio) t wl(trjio) t wh(trjio)
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4. electr ical characteristics r01ds0042ej0200 rev.2.00 page 83 of 84 sep 05, 2012 i = 0 or 1 note: 1. external pin load condition cl = 30 pf i = 0 or 1 figure 4.11 input and output timing of serial interface (i = 0 or 1) table 4.27 timing requirements of serial interface (internal clock selected as transfer clock (master communication)) symbol parameter standard unit vcc = 3v, topr = 25c vcc = 5 v, topr = 25c min. max. min. max. t d(c-q) txdi output delay time D 30 D 10 ns t su(d-c) rxdi input setup time (1) 120 D 90 D ns t h(c-d) rxdi input hold time 90 D 90 D ns table 4.28 timing requirements of serial interface (external clock selected as transfer clock (slave communication)) symbol parameter standard unit vcc = 3v, topr = 25c vcc = 5 v, topr = 25c min. max. min. max. t c(ck) clki input cycle time 300 D 200 D ns t w(ckh) clki input high width 150 D 100 D ns t w(ckl) clki input low width 150 D 100 D ns t d(c-q) txdi output delay time D 120 D 90 ns t su(d-c) rxdi input setup time 30 D 10 D ns t h(c-d) rxdi input hold time 90 D 90 D ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group 4. electr ical characteristics r01ds0042ej0200 rev.2.00 page 84 of 84 sep 05, 2012 notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high pulse width of either (1/digital filter sampling frequency 3) or the minimum va lue of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low pulse width of either (1/digital filter sampling frequency 3) or the minimum va lue of standard, whichever is greater. figure 4.12 input timing of external interrupt inti and key input interrupt kij (i = 0 to 4; j = 0 to 3) table 4.29 timing requirements of external interrupt inti (i = 0 to 4) and key input interrupt kij (j = 0 to 3) symbol parameter standard unit vcc = 3v, topr = 25c vcc = 5 v, topr = 25c min. max. min. max. t w(inh) inti input high width, kij input high width 380 (1) D 250 (1) D ns t w(inl) inti input low width, kij input low width 380 (2) D 250 (2) D ns inti input t w(inl) t w(inh) kij input
r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group appendix 1. package dimensions r01ds0042ej0200 rev.2.00 page 85 of 84 appendix 1. package dimensions diagrams showing the latest package dimensions and moun ting information are available in the ?p ackages? section of the renesas electronics website. terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nommin dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.011.8 12.2 12.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
c - 1 r8c/56e group, r8c/56f group, r8c/56g group, r8c/56h group datasheet rev. date description page summary 0.01 dec 17, 2010 ? first edition issued 0.10 mar 15, 2011 1 to 27 1. overview r8c/56f group, r8c/56g group, and r8c/56h group added 32 to 34 3.2, 3.3, and 3.4 added 46 table 3.12 port register symbol revised 0.20 sep 12, 2011 19 figure 1.6 notes 1 to 3 added 1.00 mar 28, 2012 all pages ?preliminary? and ?under development? deleted, register name changed: ?timer rd_0 elc register? ?timer rd_0 elc cooperation control register?, ?trdelc register? ?trdelccr register? register symbol name changed: ?trdelc_0? ?trdelccr_0? 2, 5, 8, 11 tables 1.1, 1.4, 1.7, and 1.10 ?minimum instruction execution time? changed 3, 6, 9, 12 tables 1.2, 1.5, 1.8, and 1.11 ?read voltage? changed 4, 7, 10, 13 tables 1.3, 1.6, 1.9, and 1.12 ?current consumption? and ?operating frequency/power supply voltage? changed 19 figure 1.6 ?p9_5/sda_1/scs_0? ?p9_5/sda_1/scs_1? 26 table 1.23 ?power supply input? changed 35, 86, 89 tables 3.1, 7.2, and 7.2.5 voltage monitor 0 circu it control register: ?after reset? changed 39 table 3.5 symbol ?trbprsc_0? added 58 table 3.24 changed, note 2 added 59 to 84 ?4. electrical characteristics? added 2.00 sep 05, 2012 2, 5, 8, 11 tables 1.1, 1.4, 1.7, and 1.10 changed 68 table 4.13 changed 70, 73 tables 4.16 and 4.19 ?v ram ? changed 71, 72 tables 4.17 and 4.18 changed 74, 75 tables 4.20 and 4.21 changed 76, 77, 81 tables 4.22 to 4.24 note 1 changed all trademarks and registered trademarks are the property of their respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
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